science

High-level verification

High-level verification is a science topic covered in the lgStudy science library. This page brings together a partial reference excerpt, illustrations, worked examples, real-world applications and a short study plan, so you can understand High-level verification rather than just read about it. In short: High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis (HLS or C synthesis), HLV is to HLS as functional verification is to logic synthesis.

Key takeaways

High-level verification belongs to science; place it in that map before memorising details.
Learn the definition first, then one example that makes the definition concrete.
Connect High-level verification to a quantity you can measure, compute or draw — that is where exam questions come from.
Reproduce the core statement of High-level verification from memory before moving on to harder problems.

Reference excerpt

High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis (HLS or C synthesis), HLV is to HLS as functional verification is to logic synthesis. Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level (RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level. In high-level synthesis, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis. Functional verification is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is of less concern today. High-level synthesis is still an emerging technology, so High-level verification today has two important areas under development

to validate HLS is correct in the translation process, i.e. to validate the design before and after HLS are equivalent, typically through formal methods to verify a design in ANSI C/C++/SystemC code is conforming to a specification, typically through logic simulation.

Terminology

History

Product areas Formal Solution: Verify high level models against RTL designs Simulation Solution: Intelligent stimulus generation, code and functional coverage, temporal assertion checker

See also Accellera Electronic system-level (ESL) Formal verification Property Specification Language (PSL) SystemC SystemVerilog Transaction-level modeling (TLM)

References 1800-2005 — IEEE Standard for System Verilog—Unified Hardware Design, Specification, and Verification Language. 2005. doi:10.1109/IEEESTD.2005.97972. ISBN 0-7381-4810-5. Accellera PSL v1.1 LRM, Accellera "Native SystemC Assertion for OCP property checking" www.nascug.org "Checking for TLM2.0 Compliance, Why bother?" www.nascug.org

External links Accellera (formerly OSCI; Open SystemC Initiative)

Worked examples

Example 1 — a first encounter with High-level verification

Start with the simplest possible case. Write down what High-level verification claims or describes in one sentence, then invent the smallest concrete situation in which that sentence is true. In science, the smallest case is usually a single object, a single equation or a single measurement. Check that every symbol or term in your sentence has a meaning in that case.

Example 2 — changing one variable

Take the situation from Example 1 and change exactly one quantity: double it, halve it, or set it to zero. Predict what should happen to High-level verification before you calculate. Comparing your prediction with the result is the fastest way to find out whether you understand the idea or only the words.

Example 3 — an exam-style question

Typical questions about High-level verification ask you to (a) state it precisely, (b) apply it to given data, and (c) explain a limitation. Practise writing all three answers in under five minutes; the third part is what separates a full-mark answer from an average one.

Applications of High-level verification

In research: High-level verification appears in science research whenever the underlying quantities have to be modelled precisely. Papers usually cite it as a starting assumption and then explore where it breaks down.
In technology and industry: Engineering practice reuses High-level verification in design rules, simulations and safety margins. Knowing the idea lets you read a specification sheet and understand why the numbers look the way they do.
In the classroom: High-level verification is common in secondary-school and first-year university syllabi. It links to neighbouring topics Electronic design automation, so understanding it makes those chapters shorter.
In everyday life: Look for High-level verification outside the textbook — in sport, cooking, traffic, electronics or the sky above you. An example you found yourself is remembered far longer than one you were given.

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How to study High-level verification in 20 minutes

Read the reference excerpt below once, without taking notes.
Close the page and write down what High-level verification means in your own words.
Compare your version with the excerpt and mark what you missed.
Work through the three examples above with pen and paper.
Explain High-level verification out loud to somebody else — or to Teacher Smith in the lgStudy chat.

Frequently asked questions

What is High-level verification in simple terms?

Why does High-level verification matter?

Because it connects several science ideas at once: it gives you a definition you can apply, a quantity you can calculate, and a way to check whether a result is plausible.

How should I study High-level verification?

Read the excerpt, restate it from memory, then work through the examples and applications listed on this page. The five-step study plan above takes about twenty minutes.

What does this page cover?

It gives you a compact reference excerpt plus original lgStudy explanations, examples, applications and study material on High-level verification.