High Bandwidth Memory (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM), initially developed by Samsung, AMD and SK Hynix. It is often used in conjunction with performance-oriented graphics accelerators, network devices, FPGAs and ASICs; some CPUs utilize HBM as on-package cache or RAM, such as the NEC SX-Aurora TSUBASA and Fujitsu A64FX. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices shipped with HBM were the AMD Fiji GPUs in 2015. HBM was adopted by JEDEC as an industry standard in October 2013. The second generation, HBM2, was accepted by JEDEC in January 2016. JEDEC officially announced the HBM3 standard on January 27, 2022, and the HBM4 standard in April 2025. In 2025, the world's largest manufacturers of HBM include SK Hynix, Samsung Electronics, and Micron Technology. TSMC produces the base die for HBM and is planned to be the foundry for several HBM companies in 2026. HBM has had an unprecedented demand increase, and in general DRAM (DDR4, DDR, and flash memory/NAND) price has in early 2026 "experienced compounded increases, some exceeding 200%, since early 2025 ... [because of] unprecedented demand coming from the AI sector ... HBM is crowding out commodity DRAM capacity. Micron noted a 3-to-1 conversion ratio between HBM and DDR5 wafer capacity, meaning every HBM ramp directly compresses general-purpose memory supply."
Technology
HBM achieves higher bandwidth than DDR4 or GDDR5 while using less power, and in a substantially smaller form factor. This is achieved by stacking up to 32 DRAM dies and an optional base die which can include buffer circuitry and test logic. The stack is often connected to the memory controller on a GPU or CPU through a substrate, such as a silicon interposer. Alternatively, the memory die could be stacked directly on the CPU or GPU chip. Within the stack the dies are vertically interconnected by through-silicon vias (TSVs) and microbumps. The HBM technology is similar in principle to, but incompatible with, the Hybrid Memory Cube (HMC) interface developed by Micron Technology. The HBM memory bus is very wide in comparison to other DRAM memories such as DDR4 or GDDR5. A HBM1 stack of four DRAM dies (4‑Hi) has two 128‑bit channels per die for a total of 8 channels and a width of 1024 bits in total. A graphics card/GPU with four 4‑Hi HBM stacks would therefore have a memory bus with a width of 4096 bits. In comparison, the bus width of GDDR memories is 32 bits, with 16 channels for a graphics card with a 512‑bit memory interface. HBM1 supported up to 4 GB per package. The larger number of connections to the memory, relative to DDR4 or GDDR5, required a new method of connecting the HBM memory to the GPU (or other processor). AMD and Nvidia have both used purpose-built semiconductor devices, called interposers, to connect the memory and GPU dies. This interposer has the added advantage of requiring the memory and processor to be physically close, decreasing memory paths. However, as semiconductor device fabrication is significantly more expensive than printed circuit board manufacture, this adds cost to the final product.
Interface
The HBM DRAM is tightly coupled to the host processor die with a distributed interface. The interface is divided into independent channels. The channels are completely independent of one another and are not necessarily synchronous to each other. HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. HBM1 DRAM used a 500 MHz differential clock CK_t / CK_c (where the suffix "_t" denotes the "true", or "positive", component of the differential pair, and "_c" stands for the "complementary" one). Commands are registered at the rising edges of CK_t and CK_c. Each channel interface maintained a 128‑bit data bus operating at this double data rate (DDR). HBM1 supported transfer rates of 1 GT/s per pin (transferring 1 bit), yielding an overall package bandwidth of 128 GB/s.
HBM2 The second generation of High Bandwidth Memory, HBM2, also specified up to eight dies per stack and doubled pin transfer rates up to 2 GT/s. Retaining 1024‑bit wide access, HBM2 was able to reach 256 GB/s memory bandwidth per package. The HBM2 spec allowed up to 8 GB per package. HBM2 was predicted to be especially useful for performance-sensitive consumer applications such as virtual reality. On January 19, 2016, Samsung announced early mass production of HBM2, at up to 8 GB per stack. SK Hynix also announced availability of 4 GB stacks in August 2016.
HBM2E In late 2018, JEDEC announced an update to the HBM2 specification, providing for increased bandwidth and capacities. Up to 307 GB/s per stack (2.5 Tbit/s effective data rate) was then supported in the official specification, though products operating at this speed had already been available. Additionally, the update added support for 12‑Hi stacks (12 dies) making capacities of up to 24 GB per stack possible. On March 20, 2019, Samsung announced their Flashbolt HBM2E, featuring eight dies per stack, a transfer rate of 3.2 GT/s, providing a total of 16 GB and 410 GB/s per stack. August 12, 2019, SK Hynix announced their HBM2E, featuring eight dies per stack, a transfer rate of 3.6 GT/s, providing a total of 16 GB and 460 GB/s per stack. On July 2, 2020, SK Hynix announced that mass production has begun. In October 2019, Samsung announced their 12-layered HBM2E.
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