The IBM System/360 architecture is the model independent architecture for the entire S/360 line of mainframe computers, including but not limited to the instruction set architecture. The elements of the architecture are documented in the IBM System/360 Principles of Operation and the IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information manuals.
Features
The System/360 architecture provides the following features:
16 32-bit general-purpose registers 4 64-bit floating-point registers 64-bit processor status register (PSW), which includes a 24-bit instruction address 24-bit (16 MB) byte-addressable memory space Big-endian byte/word order A standard instruction set, including fixed-point binary arithmetic and logical instructions, present on all System/360 models (except the Model 20, see below). A commercial instruction set, adding decimal arithmetic instructions, is optional on some models, as is a scientific instruction set, which adds floating-point instructions. The universal instruction set includes all of the above plus the storage protection instructions and is standard for some models. The Model 44 provides a few unique instructions for data acquisition and real-time processing and is missing the storage-to-storage instructions. However, IBM offered a 'Commercial Instruction Set" feature that ran in bump storage and simulated the missing instructions. The Model 20 offers a stripped-down version of the standard instruction set, limited to eight general registers with halfword (16-bit) instructions only, plus the commercial instruction set, and unique instructions for input/output. The Model 67 includes some instructions to handle 32-bit addresses and "dynamic address translation", with additional privileged instructions to provide virtual memory.
Memory Memory (storage) in System/360 is addressed in terms of 8-bit bytes. Various instructions operate on larger units called halfword (2 bytes), fullword (4 bytes), doubleword (8 bytes), quad word (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as big-endian. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified term word refers to a fullword. The original architecture of System/360 provided for up to 224 = 16,777,216 bytes of memory. The later Model 67 extended the architecture to allow up to 232 = 4,294,967,296 bytes of virtual memory.
Addressing System/360 uses truncated addressing similar to that of the UNIVAC III. That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15 general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.
Data formats The S/360 architecture defines formats for characters, integers, decimal integers and hexadecimal floating point numbers. Character and integer instructions are mandatory, but decimal and floating point instructions are part of the Decimal arithmetic and Floating-point arithmetic features.
Characters are stored as 8-bit bytes. Integers are stored as two's complement binary halfword or fullword values. Packed decimal numbers are stored as 1 to 16 8-bit bytes containing an odd number of decimal digits followed by a 4-bit sign. Sign values of hexadecimal A, C, E, and F are positive and sign values of hexadecimal B and D are negative. Digit values of hexadecimal A-F and sign values of 0-9 are invalid, but the PACK and UNPK instructions do not test for validity. Zoned decimal numbers are stored as 1 to 16 8-bit bytes, each containing a zone in bits 0-3 and a digit in bits 4-7. The zone of the rightmost byte is interpreted as a sign. Floating point numbers are only stored as fullword or doubleword values on older models. On the 360/85 and 360/195 there are also extended precision floating point numbers stored as quadwords. For all three formats, bit 0 is a sign and bits 0-7 are a characteristic (exponent, biased by 64). Bits 8-31 (8-63) are a hexadecimal fraction. For extended precision, the low order doubleword has its own sign and characteristic, which are ignored on input and generated on output.
Instruction formats Instructions in the S/360 are two, four or six bytes in length, with the opcode in byte 0. Instructions have one of the following formats:
RR (two bytes). Generally byte 1 specifies two 4-bit register numbers, but in some cases, e.g., SVC, byte 1 is a single 8-bit immediate field. RS (four bytes). Byte 1 specifies two register numbers; bytes 2-3 specify a base and displacement. RX (four bytes). Bits 0-3 of byte 1 specify either a register number or a modifier; bits 4-7 of byte 1 specify the number of the general register to be used as an index; bytes 2-3 specify a base and displacement. SI (four bytes). Byte 1 specifies an immediate field; bytes 2-3 specify a base and displacement. SS (six bytes). Byte 1 specifies two 4-bit length fields or one 8-bit length field; bytes 2-3 and 4-5 each specify a base and displacement. The encoding of the length fields is length-1. Instructions must be on a two-byte boundary in memory; hence the low-order bit of the instruction address is always 0.
Program Status Word (PSW)
The Program Status Word (PSW) contains a variety of controls for the currently operating program. The 64-bit PSW describes (among other things) the address of the current instruction being executed, condition code and interrupt masks.
Load Program Status Word (LPSW) is a privileged instruction that loads the Program Status Word (PSW), including the program mode, protection key, and the address of the next instruction to be executed. LPSW is often used to return from an interruption by loading the old PSW that is associated with the interruption class. One privileged instruction (SSM) and one unprivileged instruction (SPM) are available for manipulating subsets of the PSW without causing an interruption or loading a PSW.
Interruption system The architecture defines 5 classes of interruption. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous and asynchronous events.
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