engineering

Iddq testing

Iddq testing is a engineering topic covered in the lgStudy science library. This page brings together a partial reference excerpt, illustrations, worked examples, real-world applications and a short study plan, so you can understand Iddq testing rather than just read about it. In short: Iddq testing is a method for testing CMOS integrated circuits for the presence of manufacturing faults. It relies on measuring the supply current (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values).

Key takeaways

Iddq testing belongs to engineering; place it in that map before memorising details.
Learn the definition first, then one example that makes the definition concrete.
Connect Iddq testing to a quantity you can measure, compute or draw — that is where exam questions come from.
Reproduce the core statement of Iddq testing from memory before moving on to harder problems.

Reference excerpt

Iddq testing is a method for testing CMOS integrated circuits for the presence of manufacturing faults. It relies on measuring the supply current (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values). The current consumed in this state is commonly called Iddq for Idd (quiescent) and hence the name. Iddq testing uses the principle that in a correctly operating quiescent CMOS digital circuit, there is no static current path between the power supply and ground, except for a small amount of leakage. Many common semiconductor manufacturing faults will cause the current to increase by orders of magnitude, which can be easily detected. This has the advantage of checking the chip for many possible faults with one measurement. Another advantage is that it may catch faults that are not found by conventional stuck-at fault test vectors. Iddq testing is somewhat more complex than just measuring the supply current. If a line is shorted to Vdd, for example, it will still draw no extra current if the gate driving the signal is attempting to set it to '1'. However, a different input that attempts to set the signal to 0 will show a large increase in quiescent current, signalling a bad part. Typical Iddq tests may use 20 or so inputs. Note that Iddq test inputs require only controllability, and not observability. This is because the observability is through the shared power supply connection.

Advantages and disadvantages Iddq testing has many advantages:

It is a simple and direct test that can identify physical defects. The area and design time overhead are very low. Test generation is fast. Test application time is fast since the vector sets are small. It catches some defects that other tests, particularly stuck-at logic tests, do not. Drawback: Compared to scan chain testing, Iddq testing is time consuming, and thus more expensive, as is achieved by current measurements that take much more time than reading digital pins in mass production.

Future of Iddq testing As device geometry shrinks, i.e transistors and gates become smaller resulting in larger and more complex processors and SoCs (see Moore's law), the leakage current becomes much higher and less predictable. This makes it difficult to tell a low leakage part with a defect from a naturally high leakage part. Also, increasing circuit size means a single fault will have a lower percentage effect, making it harder for the test to detect. However, Iddq is so useful that designers are taking steps to keep it working. One particular technique that helps is power gating, where the entire power supply to each block can be switched off using a low leakage switch. This allows each block to be tested individually or in combination, which makes the tests much easier when compared to testing the whole chip.

References

Straka, B.; Manhaeve, Hans; Vanneuville, J.; Svajda, M. (1998). "A fully digital controlled off-chip IDDQ measurement unit.". Proceedings -Design, Automation and Test in Europe, DATE. Design, Automation and Test in Europe. pp. 495–500. Sabade, Sagar; Walker, D.M.H. (June 2004). "IDDX -based test methods: A survey". ACM Transactions on Design Automation of Electronic Systems. 9 (2): 159–198. doi:10.1145/989995.989997. S2CID 6401125. Retrieved 11 November 2018.

Further reading Rajsuman, Rochit (October 1994). Iddq testing for CMOS VLSI. Artech House Publishers. ISBN 0-89006-726-0. Rajsuman, Rochit (April 2000). "Iddq testing for CMOS VLSI". Proceedings of the IEEE. 88 (4): 544–568. doi:10.1109/5.843000. S2CID 2481046. (NB. This is a summary of the basic ideas behind Iddq testing, the history of the technique, and many of its characteristics.) "Iddq Tutorial" (PDF). Archived from the original (PDF) on 2007-06-07. Retrieved 2008-09-19. Available Iddq technology

Worked examples

Example 1 — a first encounter with Iddq testing

Start with the simplest possible case. Write down what Iddq testing claims or describes in one sentence, then invent the smallest concrete situation in which that sentence is true. In engineering, the smallest case is usually a single object, a single equation or a single measurement. Check that every symbol or term in your sentence has a meaning in that case.

Example 2 — changing one variable

Take the situation from Example 1 and change exactly one quantity: double it, halve it, or set it to zero. Predict what should happen to Iddq testing before you calculate. Comparing your prediction with the result is the fastest way to find out whether you understand the idea or only the words.

Example 3 — an exam-style question

Typical questions about Iddq testing ask you to (a) state it precisely, (b) apply it to given data, and (c) explain a limitation. Practise writing all three answers in under five minutes; the third part is what separates a full-mark answer from an average one.

Applications of Iddq testing

In research: Iddq testing appears in engineering research whenever the underlying quantities have to be modelled precisely. Papers usually cite it as a starting assumption and then explore where it breaks down.
In technology and industry: Engineering practice reuses Iddq testing in design rules, simulations and safety margins. Knowing the idea lets you read a specification sheet and understand why the numbers look the way they do.
In the classroom: Iddq testing is common in secondary-school and first-year university syllabi. It links to neighbouring topics Integrated circuits, so understanding it makes those chapters shorter.
In everyday life: Look for Iddq testing outside the textbook — in sport, cooking, traffic, electronics or the sky above you. An example you found yourself is remembered far longer than one you were given.

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How to study Iddq testing in 20 minutes

Read the reference excerpt below once, without taking notes.
Close the page and write down what Iddq testing means in your own words.
Compare your version with the excerpt and mark what you missed.
Work through the three examples above with pen and paper.
Explain Iddq testing out loud to somebody else — or to Teacher Smith in the lgStudy chat.

Frequently asked questions

What is Iddq testing in simple terms?

Why does Iddq testing matter?

Because it connects several engineering ideas at once: it gives you a definition you can apply, a quantity you can calculate, and a way to check whether a result is plausible.

How should I study Iddq testing?

Read the excerpt, restate it from memory, then work through the examples and applications listed on this page. The five-step study plan above takes about twenty minutes.

What does this page cover?

It gives you a compact reference excerpt plus original lgStudy explanations, examples, applications and study material on Iddq testing.