The Low Pin Count (LPC) bus is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the BIOS ROM (BIOS ROM was moved to the Serial Peripheral Interface (SPI) bus in 2006), "legacy" I/O devices (integrated into Super I/O, embedded controller, CPLD, and/or IPMI chip), and Trusted Platform Module (TPM). "Legacy" I/O devices usually include serial and parallel ports, PS/2 keyboard, PS/2 mouse, and floppy disk controller. Most PC motherboards with an LPC bus have either a Platform Controller Hub (PCH) or a southbridge chip, which acts as the host and controls the LPC bus. All other devices connected to the physical wires of the LPC bus are peripherals.
Overview
The LPC bus was introduced by Intel in 1998 as a software-compatible substitute for the Industry Standard Architecture (ISA) bus. It resembles ISA to software, although physically it is quite different. The ISA bus has a 16-bit data bus and a 24-bit address bus that can be used for both 16-bit I/O port addresses and 24-bit memory addresses; both run at speeds up to 8.33 MHz. The LPC bus uses a heavily multiplexed four-bit-wide bus operating at four times the clock speed (33.3 MHz) to transfer addresses and data with similar performance. LPC's main advantage is that the basic bus requires only seven signals, greatly reducing the number of pins required on peripheral chips. An integrated circuit using LPC will need 30 to 72 fewer pins than its ISA equivalent. This also makes the bus easier to route on crowded modern motherboards. The clock rate was chosen to match that of PCI in order to further ease integration. Also, LPC is intended to be a motherboard-only bus; there is no standardized connector in common use, though Intel defines one for use for debug modules. A small number of LPC peripheral daughterboards are available, with pinouts proprietary to the motherboard vendor: Trusted Platform Modules (TPMs), POST cards for displaying BIOS diagnostic codes, and ISA-compatible serial port peripherals for industrial use. Device discovery is not supported; since only motherboard devices or specific models of TPM are connected, the host firmware (BIOS, UEFI) image will include a static description of any devices and their I/O addresses expected to be present on a particular motherboard.
Signals LPC control signals are active-low, as indicated by the "#" symbol in their names. Signals are divided into three categories:
Unidirectional. These are driven from a single source at all times. Open-collector. These are low-speed signals which are pulled up (to the inactive state) by the host when not in use, and may be pulled down by any device. Bidirectional. These high-speed signals are actively driven high for one cycle whenever a device is done using them, after which weak pull-up resistors hold them high until another device begins using them. The LPC specification defines seven mandatory signals required for bidirectional data transfer:
LCLK (unidirectional, from host): 33.3 MHz clock. May be connected to the conventional PCI clock (PCICLK), thereby not requiring a dedicated pin on the host (south bridge). Like PCI, other signals are driven after the falling edge of LCLK, and received after the rising edge. LRESET# (open-collector): Active-low bus reset. May be connected to PCIRST#. LFRAME# (unidirectional, from host): This active-low signal indicates the beginning of an LPC bus transaction. Only the host may initiate bus transactions. LAD[3:0] (bidirectional): These four bidirectional signals carry multiplexed address, data, and other information. There are six additional signals defined, which are optional for LPC devices that do not require their functionality, but support for the first two is mandatory for the host:
LDRQ# (unidirectional, from device): DMA/bus master request. This is an output from a device that wants to perform direct memory access, either via the Intel 8237 compatible DMA controller, or the LPC-specific bus master protocol. The host must provide one corresponding input pin per device that needs it (minimum two). SERIRQ (bidirectional): Serialized Intel 8259 compatible interrupt signal. One line is shared by all LPC devices and the host. Like the LAD lines, this has a weak pull-up which will maintain it high if no device is driving it. CLKRUN# (open-collector): Signal used to restart the clock in systems that can stop it for power management. Not required if the host does not stop the clock. May be connected to the equivalent PCI signal. LPME# (open-collector): Power management event, to wake the system from a sleep state. Equivalent to the PCI bus PME# signal. LSMI# (open-collector): System management interrupt request. This is only required if an LPC device needs to trigger an SMI# in response to a bus access (e.g. to perform software emulation of a missing hardware peripheral). Otherwise, the slower SERIRQ protocol can be used to request an SMI. LPCPD# (unidirectional, from host): Optional output from the host to warn the LPC device that power is about to be removed and it should not make any interrupt or DMA requests.
… excerpt ends here. Continue reading the full article.
