The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet (i.e., 100 Mbit/s) medium access control (MAC) block to a PHY chip. The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being media independent means that different types of PHY devices for connecting to different media (i.e. twisted pair, fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. Thus, any MAC may be used with any PHY, independent of the network signal transmission medium. The MII can be used to connect a MAC to an external PHY using a pluggable connector or directly to a PHY chip on the same PCB. On older PCs, the CNR connector Type B carried MII signals. Network data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC). The original MII transfers network data using 4-bit nibbles in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve 100 Mbit/s throughput. The original MII design has been extended to support reduced signals and increased speeds. The abbreviation xMII stands for generic media-independent interface, which includes:
Reduced media-independent interface (RMII) Gigabit media-independent interface (GMII) Reduced gigabit media-independent interface (RGMII) Serial media-independent interface (SMII) Serial gigabit media-independent interface (serial GMII, SGMII) High serial gigabit media-independent interface (HSGMII) Quad serial gigabit media-independent interface (QSGMII) Penta serial gigabit media-independent interface (PSGMII) 10-gigabit media-independent interface (XGMII) The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.
Standard MII The standard MII features a small set of registers:
The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bit field with the following information:
Transmitter signals
The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s, 2.5 MHz for 10 Mbit/s). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle. Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY. More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an EEE-capable PHY to enter low power mode.
Receiver signals
The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute. The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost. Similar to transmit, raising RX_ER outside a frame is used for special signaling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a false carrier indication. The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists. In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as an indication of an absent or disconnected PHY.
Management signals
MDC and MDIO constitute a synchronous serial data interface similar to I²C. As with I²C, the interface is a multidrop bus so MDC and MDIO can be shared among multiple PHYs.
Limitations The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.
Reduced media-independent interface
Reduced media-independent interface (RMII) is a standard that was developed to reduce the number of signals required to connect a PHY to a MAC. This helps reduce cost and complexity for network hardware, especially in the context of microcontrollers with built-in MAC, FPGAs, multiport switches or repeaters, and PC motherboard chipsets. The following changes from the MII standard cut the number of required signals from 18 in half to only 9:
MII's two clocks (TXCLK and RXCLK) are replaced by a single clock (REF_CLK) used as a reference for both receiver and transmitter signals. The clock frequency is doubled from 25 MHz to 50 MHz, while both data paths are halved from 4 bits to 2 bits. Data is clocked out 2 bits at a time (vs 4 bits at a time in MII) or 1 bit at a time for serial network interface (SNI) mode (10 Mbit/s only). Data is still sampled on the rising edge only (i.e., it is not double-pumped). RXDV and CRS signals are multiplexed into one signal. The COL signal is removed. RX_ER became optional. Additionally, on multiport devices (such as a switch), MDIO, MDC, and REF_CLK may be shared, leaving 6 or 7 pins per port.
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