Memory management unit

A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit that examines all references to memory, and translates the memory addresses being referenced, known as virtual memory addresses, into physical addresses in main memory. In modern systems, programs generally have addresses that access the theoretical maximum memory of the computer architecture, 32 or 64 bits. The MMU maps the addresses from each program into separate areas in physical memory, which is generally much smaller than the theoretical maximum. This is possible because programs rarely use large amounts of memory at any one time. Most modern operating systems (OS) work in concert with an MMU to provide virtual memory (VM) support. The MMU tracks memory use in fixed-size blocks known as pages. If a program refers to a location in a page that is not in physical memory, the MMU sends an interrupt to the operating system. The OS selects a lesser-used block in memory, writes it to backing storage such as a hard drive if it has been modified since it was read in, reads the page from backing storage into that block, and sets up the MMU to map the block to the originally requested page so the program can use it. This is known as demand paging. Some simpler real-time operating systems do not support virtual memory and do not need an MMU, but still need a hardware memory protection unit. MMUs generally provide memory protection to block attempts by a program to access memory it has not previously requested, which prevents a misbehaving or malicious program from modifying or reading data belonging to another program. In some early microprocessor designs, memory management was performed by a separate integrated circuit such as the VLSI Technology VI475 (1986), the Motorola 68851 (1984) used with the Motorola 68020 CPU in the Macintosh II, or the Z8010 and Z8015 (1985) used with the Zilog Z8000 family of processors. Later microprocessors (such as the Motorola 68030 and the Zilog Z280) placed the MMU together with the CPU on the same integrated circuit, as did the Intel 80286 and later x86 microprocessors. Some early systems, especially 8-bit systems, used very simple MMUs to perform bank switching.

Types of address translation Early systems used base and bounds addressing that further developed into segmentation, or used a fixed set of blocks instead of loading them on demand. The difference between these two approaches is the size of the contiguous block of memory; paged systems break up main memory into a series of equal-sized blocks, while segmented systems generally allow for variable sizes.

Segmented translation In segmented translation, a memory address contains a segment number and an offset within the segment. Segments are variable-length and may have permissions, such as read, write, and execute, associated with them. A segment is loaded into a contiguous area of physical memory. Typically, the segment number is used as an index into a segment table; each entry in the segment table holds the address of the area of physical memory, the length of the segment, and other information such as permission flags. This style has the advantage of simplicity; the memory blocks are continuous, and thus only the two values, base and limit, need to be stored for mapping purposes. The disadvantage of this approach is that it leads to an effect known as external fragmentation. This occurs when memory allocations are released but are non-contiguous. In this case, enough memory may be available to handle a request, but this is spread out and cannot be allocated to a single segment. On systems where programs start and stop over time, this can eventually lead to memory being highly fragmented and no large blocks remaining; in this case, segments would need to be moved in memory, and their segment table entries modified to reflect the new physical address, to make a contiguous space large enough for a segment available. Some models of the PDP-11 16-bit minicomputer have a segmented memory management unit with a set of page address registers (PARs) and page description registers (PDRs); this maps a 16-bit virtual address to an 18-bit physical address. The PDP-11/70 expands that to produce a 22-bit physical address. Segmenting was widely used on microcomputer platforms of the 1980s. Among the MMUs that used this concept were the Motorola 68451 and the Zilog Z8010, but many other examples exist. The Intel 8086, Intel 8088, Intel 80186, and Intel 80188 provide crude memory segmentation and no memory protection. (Every byte of every segment is always available to any program.) The 16-bit segment registers allow for 65,536 segments; each segment begins at a fixed offset equal to 16 times the segment number; the segment starting address granularity is 16 bytes. Each segment grants read-write access to 64 KiB (65,536 bytes) of address space (this limit is set by the 16-bit PC and SP registers; the processor does no bounds checking). Offset+address exceeding 0xFFFFF wraps around to 0x00000. Each 64 KiB segment overlaps the next 4,095 segments; each physical address can be denoted by 4,096 segment–offset pairs. This scheme can address only 1 MiB (1024 KiB) of physical memory (and memory-mapped i/o). (Optional expanded memory hardware can add bank-switched memory under software control.) Later x86 processors, starting with the Intel 80286, supported real segmented mapping, with a segment table.

Paged translation

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