Negative-bias temperature instability (NBTI) is a key reliability issue in MOSFETs, a type of transistor aging. NBTI manifests as an increase in the threshold voltage and consequent decrease in drain current and transconductance of a MOSFET. The degradation is often approximated by a power-law dependence on time. It is of immediate concern in p-channel MOS devices (pMOS), since they almost always operate with negative gate-to-source voltage; however, the very same mechanism also affects nMOS transistors when biased in the accumulation region, i.e. with a negative bias applied to the gate. More specifically, over time positive charges become trapped at the oxide-semiconductor boundary underneath the gate of a MOSFET. These positive charges partially cancel the negative gate voltage without contributing to conduction through the channel as electron holes in the semiconductor are supposed to. When the gate voltage is removed, the trapped charges dissipate over a time scale of milliseconds to hours. The problem has become more acute as transistors have shrunk, as there is less averaging of the effect over a large gate area. Thus, different transistors experience different amounts of NBTI, defeating standard circuit design techniques for tolerating manufacturing variability which depend on the close matching of adjacent transistors. NBTI has become significant for portable electronics because it interacts badly with two common power-saving techniques: reduced operating voltages and clock gating. With lower operating voltages, the NBTI-induced threshold voltage change is a larger fraction of the logic voltage and has a higher potential to disrupts operations. When a clock is gated off, transistors stop switching and NBTI effects accumulate much more rapidly. When the clock is re-enabled, the transistor thresholds have changed and the circuit may not operate. Some low-power designs switch to a low-frequency clock rather than stopping completely in order to mitigate NBTI effects. There is also a positive bias temperature instability (PBTI) which affects a nMOS transistor when positively biased. It has become more important with the introduction of high κ metal gates.
Physics The details of the mechanisms of NBTI have been debated, but two effects are believed to contribute: trapping of positively charged holes, and generation of interface states.
preexisting traps located in the bulk of the dielectric are filled with holes coming from the channel of pMOS. Those traps can be emptied when the stress voltage is removed, so that the Vth degradation can be recovered over time. interface traps are generated, and these interface states become positively charged when the pMOS device is biased in the "on" state, i.e. with negative gate voltage. Some interface states may become deactivated when the stress is removed, so that the Vth degradation can be recovered over time. The existence of two coexisting mechanisms has resulted in scientific controversy over the relative importance of each component, and over the mechanism of generation and recovery of interface states. In sub-micrometer devices nitrogen is incorporated into the silicon gate oxide to reduce the gate leakage current density and prevent boron penetration. It is known that incorporating nitrogen enhances NBTI. For new technologies (45 nm and shorter nominal channel lengths), high-κ metal gate stacks are used as an alternative to improve the gate current density for a given equivalent oxide thickness (EOT). Even with the introduction of new materials like hafnium oxide in the gate stack, NBTI remains and is often exacerbated by additional charge trapping in the high-κ layer. In the case of PBTI, no interface states are generated and 100% of the Vth degradation may be recovered.
Modeling approaches NBTI modeling approaches can be broadly classified as empirical or physics-based. The empirical power-law model is widely used due to its simplicity and simulation efficiency. It approximates the threshold voltage shift as:
Δ V th ( t ) = A ⋅ t n {\displaystyle \Delta V_{\text{th}}(t)=A\cdot t^{n}}
where A {\displaystyle A} is a prefactor influenced by electric field, oxide thickness, temperature, and process variation, and n {\displaystyle n} is the time exponent. While useful for estimating long-term aging trends, this model lacks physical insight into trap generation and does not account for recovery. The reaction–diffusion (RD) model is more computationally intensive but provides improved accuracy and predictive capabilities, especially in advanced nodes and for time-dependent recovery. This more physically accurate model describes two interlinked processes as per
Reaction phase Under negative bias and elevated temperature, a chemical reaction at the Si/SiO₂ interface breaks Si–H bonds, generating interface traps and releasing hydrogen:
Si–H ⇌ Si + + X interface {\displaystyle {\text{Si–H}}\rightleftharpoons {\text{Si}}^{+}+X_{\text{interface}}} (1) The forward rate constant k f {\displaystyle k_{f}} governs the rate of trap generation.
Diffusion phase The freed hydrogen diffuses away into the oxide bulk, reducing the local hydrogen concentration and triggering further Si–H dissociation. Upon stress removal, some hydrogen returns to re-passivate the traps:
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