The OpenROAD Project (Open Realization of Autonomous Design) is a major open-source project that aims to provide a fully automated, end-to-end digital integrated circuit design flow (RTL-to-GDSII), thereby eliminating the need for human intervention. The project, led by UC San Diego, aims to democratize hardware design and promote rapid innovation in integrated circuit (IC) design by reducing barriers related to cost, time, and experience. OpenROAD was started in 2018 to address the high cost, needed experience, and unpredictability of conventional EDA tools as part of DARPA's IDEA initiative. Its goal is to establish a 24-hour, no-human-in-loop (NHIL) flow that matches the usual quality of design, and produces layouts directly suitable for manufacturing. OpenROAD is released under a permissive BSD license to keep it freely available, despite the inclusion of commercial tools. Among OpenROAD's main features are scripting interfaces (Tcl/Python) and a common database (OpenDB), which help designers automate or personalize every phase of the digital design process. Projects using the flow range from Hammer at the University of California, Berkeley, to the FASoC analog/mixed-signal flow to the Zero-ASIC Silicon Compiler. Readymade open ASIC flows include OpenLane and OpenROAD scripts.
History and motivation Modern digital integrated circuit design is a complex, multi-stage process that requires specialized, expensive, and proprietary tools along with expertise in tuning their parameters. DARPA's IDEA program under Andreas Olofsson initiated OpenROAD, an autonomous, open-source RTL-to-GDSII flow designed to address the "design cost crisis" by eliminating the need for expert tinkering and licensing, thereby democratizing chip design and enabling smaller companies, research groups, and academic institutions to produce semiconductor layouts. The aim was to create a no-human-in-loop flow that could take an RTL description and generate a GDSII mask-ready layout in under 24 hours, with performance, power, and area (PPA) equivalent to commercial design processes. OpenROAD was led by UC San Diego professor Andrew Kahng. It is supported by commercial partners Arm, Qualcomm, SkyWater, and others. The first iteration (v1.0, 2020) of a current FinFET technology (GF12LP, ~12 nm) produced a complete, integrated flow producing DRC-clean layouts. Along with an almost complete technology-node enhancement in PPA, Version 2.0 (2021) includes advanced capabilities (RC extraction, chip-package co-design). Hundreds of designs on the open SkyWater 130 nm PDK (complete with a Google MPW shuttle) and experimental runs on Intel 22 nm FinFET in 2021 have helped the community improve the flow over time. Forming the foundation of the OpenLane and ChipIgnite projects, the open-source ecosystem for RISC-V System-on-Chip (SoC) designs has expanded rapidly and is now considered the leading open-source physical design infrastructure for digital integrated circuits. Through university courses and events such as the 7 nm OpenROAD Design Challenge, which aim to increase the user base, the initiative aggressively promotes worker education and training.
Design philosophy and architectural technique The keystones of the OpenROAD design philosophy are openness and automation. Its architecture is built on a shared in-memory design database and modular engines, each of which runs a step of the flow. Created by Athena Design Systems and turned open-source for this project, all of the tools share a common OpenDB data model and transmit data over standard LEF/DEF (and its binary variants). For RTL-to-GDS, designers can employ an autonomous OpenROAD flow script (ORFS) pipeline, or, for extra control, they can call certain stages using Tcl/Python commands driven by scripts. OpenROAD is, therefore, not just a reference autonomous flow but also a versatile platform for customized flows or research. The OpenROAD design forms a single EDA platform, as all essential RTL-to-GDSII processes are carried out by modules sharing a common database. Its open design lets new methods (machine learning (ML)-based tuning, GPU acceleration, etc.) be quickly incorporated and supports research and teaching, even as it continually optimizes to match industry power-to-performance (PPA) ratios. The fundamental ideas are:
No-Human-In-Loop (NHIL) The instruments are designed to run free from human direction. For example, OpenROAD's AutoTuner, a machine-learning architecture, methodically explores tool settings, thereby reducing the need for expert hand-tuning.
Integrated Data Model All tools save the design in an Open Database (OpenDB). OpenDB is hierarchical (it allows any cell hierarchy), rich in EDA features such as net connections, layout geometry, and timing, and compatible with LEF/DEF. This means that any step can query or modify the chip data without incurring the expense of file I/O. For example, placement results can be transmitted immediately to clock tree synthesis, or in-memory parasitics from routing can be reported back to static timing analysis.
Extensibility and Scripting Every OpenROAD component is assessable through a Tcl command, such as clock_tree_synthesis, location, and route, that can embody scripting and extensions. A Python API, package OpenROAD-OpenDbPy, allows the same access from Python. This allows users to integrate OpenROAD into more general tool flows or construct their own design scripts. Designers can use the API to handle chores not native to OpenROAD, such as symmetric placements or customized power grid generation.
Continual Integration and Quality OpenROAD utilizes Jenkins on Google Cloud to maintain a rigorous Continuous Integration (CI) pipeline, to catch errors and omissions as soon as possible. New designs, including genuine MPW projects and code analysis tools (like Coverity and code sanitizers), check for mistakes and are often used in regression tests. This focus on automation and testing enables early error identification and stability across a wide range of user designs.
… excerpt ends here. Continue reading the full article.
