PICA200 is a graphics processing unit (GPU) designed by Digital Media Professionals Inc. (DMP), a Japanese GPU design startup company, for use in embedded devices such as vehicle systems, mobile phones, cameras, and game consoles. The PICA200 is an IP Core which can be licensed to other companies to incorporate into their SOCs. It was most notably licensed for use in the Nintendo 3DS. It was announced at SIGGRAPH 2005, and an operational demo, "Mikage", was presented in collaboration with Futuremark at SIGGRAPH 2006.
Overview The PICA200 is the successor to the ULTRAY2000, a proof of concept graphics workstation presented at SIGGRAPH 2005, created with the goal of testing DMP's attempts at a low power fixed-function "MAESTRO" GPU architecture. The PICA200 implements the "MAESTRO-2G" architecture and supports programmable vertex shaders and geometry shaders, with a fixed-function fragment stage. It is advertised as supporting OpenGL ES 1.1 with certain proprietary extensions. The PICA200 has up to 4 programmable vertex processors which can work in parallel. One of those processors, the "primitive engine", can be used as either vertex processor or a geometry processor. The "primitive engine" also allows the ability to do more complex operations including, but not limited to Catmull–Clark subdivision and Loop subdivision Some MAESTRO-2G extensions include, per-pixel lighting (where the lighting is calculated per pixel instead of per vertex), procedural texture generation, bidirectional reflectance distribution function (BRDF), Cook-Torrance specular highlights, polygon subdivision (through geometry shaders), soft shadow projection, and fake subsurface scattering (similar to two-sided lighting).
Applications The PICA200 is used as the GPU for the Nintendo 3DS portable handheld game console. PICA200 was also incorporated into the NV7 3D/2D graphics LSI, which was announced mainly for amusement equipment and later reported as part of an embedded 3D graphics platform aimed at arcade and digital-signage systems.
Specification Manufacturing process: 65 nm Maximum clock frequency 400 MHz Pixel performance (theoretical): 400 Megapixel/s @100 MHz 800 Megapixel/s @200 MHz Vertex performance (theoretical): 40Mtriangle/s @100 MHz 15.3Mpolygon/s @200 MHz Power consumption: 0.5-1.0 mW/MHz Frame Buffer max. 4095×4095 pixels Supported pixel formats: RGBA4444, RGB565, RGBA5551, RGBA8888 Vertex program (ARB_vertex_program) Render to Texture Hardware Transform and Lighting(T&L) MipMap Bilinear texture filtering Alpha blending Full-scene anti-aliasing (2×2) Phong Shading Cel Shading Perspective-Correct Texture Mapping Dot3 Bump Mapping/Normal Mapping. Shadow Mapping Shadow Volumes Self-Shadowing Light-mapping Environment Mapping/Reflection Mapping Volumetric Fog Post-processing effects like motion, bloom, depth of field, HDR rendering, gamma correction Polygon offset Depth Test, Stencil Test, Alpha Test. Clipping, Culling 8-bit stencil buffer 24-bit depth buffer Single/Double/Triple buffer 5-Stage TEV Pipeline TEV Combiner Buffer(Only the first four TEV stages can write to the combiner buffer) Color Combiners, Alpha Combiners, Texture Combiners. DMP's MAESTRO-2G technology: Per-pixel lighting Fake sub-surface scattering Procedural texture Refraction mapping Subdivision primitive Shadow Gaseous object rendering Bidirectional reflectance distribution function Cook-Torrance Model Polygon subdivision Soft shadowing
References
External links PICA200 3D Graphics IP PICA200 block diagram SIGGRAPH 2006 - 日本発のGPUテクノロジー「PICA200」が公開 (August 15, 2006) ニンテンドー3DSにDMPの3DグラフィックスIPコア「PICA200」が採用された理由 (June 22, 2010)
