The PIC instruction set is the set of instructions that Microchip Technology PIC or dsPIC microcontroller supports. The instructions are usually programmed into the Flash memory of the processor, and automatically executed by the microcontroller on startup. PICmicro chips have a Harvard architecture and instruction words have unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits. They are accumulator machines, with a common accumulator "W" being one operand in all 2-operand instructions. In the instruction set tables that follow, register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". Arithmetic instructions write their result to one of the inputs selected by the "d" bit: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.
Architecture Memory operands are also referred to as "registers". Most are simply general-purpose storage (RAM), while some locations are reserved for special function registers. Except for a single accumulator (called W), almost all other registers are memory-mapped, even registers like the program counter and ALU status register. (The other exceptions, which are not memory-mapped, are the return address stack, and the tri-state registers used to configure the GPIO pins.) Some arithmetic instructions only use one of their inputs, but still use a dbit. For example, MOVW copies the value of W to the destination. When used with d = 1, this stores W to f. There is a matching MOVF instruction which outputs the value of f. When used with d = 0, this loads f into W. When used with d = 1, the only visible effect is to set the zero flag depending on the value of f. The instruction set does not contain conditional branch instructions. Instead, it contains conditional skip instructions which cause the following instruction to be ignored. A conditional skip followed by an unconditional branch performs a conditional branch. The skip instructions test any bit of any register. The ALU status register is one possibility. Memory operands are specified by absolute address; the location is fixed at compile time. To provide indirect addressing, a pair of special function registers are provided:
The file select register (FSR) is written with the address of the desired memory operand, after which The indirect file register (INDF) becomes an alias for the operand pointed to by the FSR. This mechanism also allows up to 256 bytes of memory to be addressed, even when the instruction set only allows 5- or 7-bit absolute addresses. Models with more registers (special function registers plus RAM) than fit into the instruction provide multiple banks of memory, and use one of two mechanisms for accessing them:
Most baseline core devices, and some mid-range core devices, use the high-order bits of the file select register to select the current register bank. More recent models have a separate bank select register, and a MOVLB instruction to set it. PIC processors with more than 256 words of program use paged memory. The internal program counter and return stack are as wide as necessary to address all memory, but only the low 8 bits are visible to software in the PCL ("PC low") register. There is an additional PCLATH ("PC latch high") register which is only modified by software. Any operation which does not specify the full destination address (such as a 9-bit GOTO or an 8-bit write to the PCL register) fills in the additional high bits from the corresponding part of PCLATH. (Some PIC18 processors extend this beyond 16 bits with a PCLATU register to supply bits 16–23.)
Baseline core devices (12 bit) This is the original 1976 instruction set, introduced in the General Instrument PIC1640 and PIC1650, with the only additions since then being the miscellaneous instructions other than NOP.
*: Extended instruction, not available on most 12-bit PICs. Of the models with extended RAM, most (e.g. 16C5x, 16F5x) extend the register address space using the high-order bits of the FSR. A few (e.g. PIC12F529T39A) have a separate bank select register which can be set with this instruction. †: Extended instruction, only available on "enhanced baseline" PICs. Only the very few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack) include these instructions. All such models also include MOVLB.
General Instrument PIC1670 (13 bit, obsolete) Introduced in 1979, this expanded PIC supported 64 bytes of register space (16 special function registers and 48 bytes of RAM), 1024 words of ROM, a 6-level hardware stack, and interrupt handling. The PIC1665 was a variant with external ROM used for developing firmware for the mask ROM 1670. It added a signed overflow bit to the status register (bit 3). Status register bits 4 and 5 provided read-only access to the high 2 bits of the 10-bit program counter. The instruction set is mostly the same as the 12-bit PIC with the address field enlarged. However, the 8-bit immediate instructions gain an additional opcode bit. Rather than adding an additional four instructions with an 8-bit immediate operand, the instruction set adds two instructions with 8-bit operands, two instructions with 7-bit operands (6-bit address plus direction bit), and four instructions with 6-bit operands (6-bit address):
The 8-bit immediate group grows to 6 instructions by adding ADDLW and RETLW. The latter is moved out of the control transfer group, allowing a full 10-bit address in the CALL instruction. The ALU operations group gains add/subtract with carry (ADCWF, SUBBWF) instructions (7-bit operands). The CLRW instruction is deleted (it wastes a 6-bit memory address and duplicates MOVLW 0). Five new instructions with a 6-bit memory address operands are added. These do not have a destination select bit, and include three "compare and skip" instructions which do not write a result, and two "rotate without carry" instructions. This instruction set is not used in any currently manufactured part and is of historical interest only.
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