In digital signal processing (DSP), parallel processing is a technique duplicating function units to operate different tasks (signals) simultaneously. Accordingly, we can perform the same processing for different signals on the corresponding duplicated function units. Further, due to the features of parallel processing, the parallel DSP design often contains multiple outputs, resulting in higher throughput than not parallel.
Conceptual example Consider a function unit ( F 0 {\displaystyle F_{0}} ) and three tasks ( T 0 {\displaystyle T_{0}} , T 1 {\displaystyle T_{1}} , and T 2 {\displaystyle T_{2}} ). The required time for the function unit F 0 {\displaystyle F_{0}} to process those tasks is t 0 {\displaystyle t_{0}} , t 1 {\displaystyle t_{1}} , and t 2 {\displaystyle t_{2}} , respectively. Then, if we operate these three tasks in a sequential order, the required time to complete them is t 0 + t 1 + t 2 {\displaystyle t_{0}+t_{1}+t_{2}} .
However, if we duplicate the function unit to another two copies ( F {\displaystyle F} ), the aggregate time is reduced to m a x ( t 0 , t 1 , t 2 ) {\displaystyle max(t_{0},t_{1},t_{2})} , which is smaller than in a sequential order.
Versus pipelining Mechanism:
Parallel: duplicated function units working in parallel Each task is processed entirely by a different function unit. Pipelining: different function units working in parallel Each task is split into a sequence of sub-tasks, which are handled by specialized and different function units. Objective:
Pipelining leads to a reduction in the critical path, which can increase the sample speed or reduce power consumption at the same speed, yielding higher performance per watt. Parallel processing techniques require multiple outputs, which are computed in parallel in a clock period. Therefore, the effective sample speed is increased by the level of parallelism. Consider a condition that we are able to apply both parallel processing and pipelining techniques, it is better to choose parallel processing techniques with the following reasons
Pipelining usually causes I/O bottlenecks Parallel processing is also utilized for reduction of power consumption while using slow clocks The hybrid method of pipelining and parallel processing further increase the speed of the architecture
Parallel FIR filters Consider a 3-tap FIR filter:
y ( n ) = a x ( n ) + b x ( n − 1 ) + c x ( n − 2 ) {\displaystyle y(n)=ax(n)+bx(n-1)+cx(n-2)}
which is shown in the following figure. Assume the calculation time for multiplication units is Tm and Ta for add units. The sample period is given by
T sample ≥ T m + 2 T a {\displaystyle T_{\text{sample}}\geq T_{m}+2T_{a}}
By parallelizing it, the resultant architecture is shown as follows. The sample rate now becomes
T sample ≥ T clock N = T m + 2 T a 3 {\displaystyle T_{\text{sample}}\geq {\frac {T_{\text{clock}}}{N}}={\frac {T_{m}+2T_{a}}{3}}}
where N represents the number of copies. Please note that, in a parallel system, T sample ≠ T clock {\displaystyle T_{\text{sample}}\neq T_{\text{clock}}} while T sample = T clock {\displaystyle T_{\text{sample}}=T_{\text{clock}}} holds in a pipelined system.
Parallel 1st-order IIR filters Consider the transfer function of a 1st-order IIR filter formulated as
H ( z ) = z − 1 1 − a z − 1 {\displaystyle H(z)={\frac {z^{-1}}{1-az^{-1}}}}
… excerpt ends here. Continue reading the full article.
