A permuted congruential generator (PCG) is a pseudorandom number generation algorithm developed in 2014 by Dr. M.E. O'Neill which applies an output permutation function to improve the statistical properties of a modulo-2n linear congruential generator (LCG). It achieves excellent statistical performance with small and fast code, and small state size. LCGs with a power-of-2 modulus are simple, efficient, and have uniformly distributed binary outputs, but suffer from a well-known problem of short periods in the low-order bits. A PCG addresses this by adding an output transformation between the LCG state and the PCG output. This adds two elements to the LCG:
if possible, the LCG modulus and state is expanded to twice the size of the desired output, so the shortest-period state bits do not affect the output at all, and the most significant bits of the state are used to select a bitwise rotation or shift which is applied to the state to produce the output. The variable rotation ensures that all output bits depend on the most-significant bit of state, so all output bits have full period.
Variants The PCG family includes a number of variants. The core LCG is defined for widths from 8 to 128 bits, although only 64 and 128 bits are recommended for practical use; smaller sizes are for statistical tests of the technique. The additive constant in the LCG can be varied to produce different streams. The constant is an arbitrary odd integer, so it does not need to be stored explicitly; the address of the state variable itself (with the low bit set) can be used. There are several different output transformations defined. All perform well, but some have a larger margin than others. They are built from the following components:
RR: A random (input-dependent) rotation, with output half the size of input. Given a 2b-bit input word, the b−1 most significant bits are used for the rotate amount, the next-most-significant 2b−1 bits are rotated right and used as the output, and the low 2b−1+1−b bits are discarded. RS: A random (input-dependent) shift, for cases where rotates are more expensive. Again, the output is half the size of the input. Beginning with a 2b-bit input word, the most significant b−3 bits are used for a shift amount, which is applied to the next-most-significant 2b−1+2b−3−1 bits, and the least significant 2b−1 bits of the result are output. The low 2b−1−2b−3−b+4 bits are discarded. XSH: An xorshift operation, x ^= x >> constant. The constant is chosen to be half of the bits (rounded down) not discarded by the following RR or RS operation. XSL: A simplified version of xorshift, folding the value in half by XORing the high half into the low. The folded value is used for subsequent rotations. RXS: An xorshift by a variable (input-dependent) amount. The most significant b−2 bits are used to select a shift amount between b−2 and 2b−2+b−3. M: A multiply by a fixed constant. Each of these operations is either invertible (and thus one-to-one) or a truncation (and thus 2k-to-one for some fixed k), so their composition maps the same fixed number of input states to each output value. This preserves the equidistribution of the underlying LCG. These are combined into the following recommended output transformations, illustrated here in their most common sizes:
XSH-RR: An xorshift mixes some high-order bits down, then bits 63–59 select a rotate amount to be applied to bits 27–58. (64→32 bits) count = (int)(x >> 59); x ^= x >> 18; return rotr32((uint32_t)(x >> 27), count);. XSH-RS: Similar, but fewer bits select the shift amount. (64→32 bits) count = (int)(x >> 61); x ^= x >> 22; return (uint32_t)(x >> (29 - count));. XSL-RR: A simplified version of XSH-RR, this is optimized for 128-bit states implemented using two words on 64-bit machines. (128→64 bits) count = (int)(x >> 122); x64 = (uint64_t)(x ^ (x >> 64)); return rotr64(x64, count); RXS-M-XS: The slowest and strongest output transformation when used to produce half-size output, this becomes the weakest when used as intended, to produce an output the same size as the state. For use when the state size must be limited to 32 or 64 bits. (32→32 bits) count=(int)(x >> 28); x ^= x >> (4 + count); x *= 277803737u; return x ^ (x >> 22); (64→64 bits) count=(int)(x >> 59); x ^= x >> (5 + count); x *= 12605985483714917081u; return x ^ (x >> 43); XSL-RR-RR: Similar to the preceding, this turns 128 bits of state into 128 bits of output, when the application demands it. (128→128 bits) count = (int)(x >> 122); low64 = rotr64((uint64_t)(x ^ (x >> 64)), count); high64 = rotr64((uint64_t)(x >> 64), low64 & 63); return (uint128_t)high64 << 64 | low64; Finally, if a generator period longer than 2128 is required, the generator can be extended with an array of sub-generators. One is chosen (in rotation) to be added to the main generator's output, and every time the main generator's state reaches zero, the sub-generators are cycled in a pattern which provides a period equal to 2 to the power of the total state size.
Example code The generator recommended for most users is PCG-XSH-RR with 64-bit state and 32-bit output. It can be implemented as:
The generator applies the output transformation to the initial state rather than the final state in order to increase the available instruction-level parallelism to maximize performance on modern superscalar processors. A slightly faster version eliminates the increment, reducing the LCG to a multiplicative (Lehmer-style) generator with a period of only 262, and uses the weaker XSH-RS output function:
The time saving is minimal, as the most expensive operation (the 64×64-bit multiply) remains, so the normal version is preferred except in extremis. Still, this faster version also passes statistical tests. When executing on a 32-bit processor, the 64×64-bit multiply must be implemented using three 32×32→64-bit multiply operations. To reduce that to two, there are 32-bit multipliers which perform almost as well as the 64-bit one, such as 0xf13283ad, 0xffffffff0e703b65 or 0xf2fc5985.
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