In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components. This geometric representation is called an integrated circuit layout. This step is usually split into several sub-steps, which include both design and verification and validation of the layout. Modern day Integrated Circuit (IC) design is split up into Front-end Design using HDLs and Back-end Design or Physical Design. The inputs to physical design are (i) a netlist, (ii) library information on the basic devices in the design, and (iii) a technology file containing the manufacturing constraints. Physical design is usually concluded by Layout Post Processing, in which amendments and additions to the chip layout are performed. This is followed by the wafer fabrication, the manufacturing process whereby designs are transferred via photomasks onto silicon dies which are then packaged into ICs. Each of the phases mentioned above has design flows associated with them. These design flows lay down the process and guide-lines/framework for that phase. The physical design flow uses the technology libraries that are provided by the fabrication houses. These technology files provide information regarding the type of silicon wafer used, the standard cells used, the layout rules (like DRC in VLSI), etc. The physical design engineer (sometimes called physical engineer or physical designer) is responsible for the design and layout (routing), specifically in ASIC/FPGA design.
Divisions Typically, the IC physical design is categorized into full custom, semi-custom, gate array, and FPGA design.
Full-Custom: Designer has full flexibility on the layout design; predefined cells may or may not be used. The designer has full control over both the design and placement of the cells, and over the routing connecting them. Semi-Custom: Pre-designed library cells (preferably tested with DFM) are used, and the designer has flexibility in placement of the cells and routing. Gate array (and similar technologies): The library cells are fixed, and possibly pre-fabricated. The designer controls only the routing. Field-programmable gate array (FPGA): Both the cell library and the routing are fixed. The designer controls the settings of switches that connect various logic units to the pre-defined wires. The design flow used depends strongly on the requirements. Full custom design is the slowest and most expensive, but offers potentially the highest performance. Semi-custom or ASIC is somewhat easier as the components have been pre-characterized, although in some cases the designer has the flexibility to design/modify design blocks from vendor provided libraries in ASIC. This flexibility is missing for flows using FPGAs (e.g. Altera or Xilinx), which are the easiest to implement, as the chips are already fabricated. These offer the advantage of no fabrication time (a chip designed today can be running tomorrow) and by far the easiest debugging, but have the lowest performance and the highest cost per gate.
ASIC physical design flow
The main steps in the ASIC physical design flow are, starting with the post-synthesis netlist:
Floorplanning Partitioning Placement Clock-tree Synthesis (CTS) Routing Physical Verification Layout Post Processing with Mask data preparation These steps are just the basics. There are detailed PD flows that are used depending on the tools used and the methodology/technology. Some of the tools/software commonly used in the back-end design are:
Cadence (Cadence Encounter RTL Compiler, Encounter Digital Implementation, Cadence Voltus IC Power Integrity Solution, Cadence Tempus Timing Signoff Solution) Synopsys (Design Compiler, IC Compiler II, IC Validator, PrimeTime, PrimePower, PrimeRail) Magma (BlastFusion, etc.) Mentor Graphics (Olympus SoC, IC-Station, Calibre) The ASIC physical design flow uses the technology libraries that are provided by the fabrication houses. Technologies are commonly classified according to minimal feature size. Standard sizes, in the order of miniaturization, are 2μm, 1μm, 0.5μm, 0.35μm, 0.25μm, 180nm, 130nm, 90nm, 65nm, 45nm, 28nm, 22nm, 18nm, 14nm, etc. They may be also classified according to major manufacturing approaches: n-Well process, twin-well process, SOI process, etc.
Design netlist Physical design is based on a netlist which is the end result of the logic synthesis process. Synthesis converts the RTL design, usually coded in VHDL or Verilog HDL, to gate-level descriptions which the next set of tools can read and understand. This netlist contains information on the cells used, their interconnections, area used, and other details. Typical synthesis tools are:
Cadence RTL Compiler/Build Gates/Physically Knowledgeable Synthesis (PKS) Synopsys Design Compiler During the synthesis process, constraints are applied to ensure that the design meets the specified functionality and speed. Only after the netlist is verified for functionality and timing it is sent for the physical design flow. Note however that timing at this point is only an estimate, as the parasitics from the physical design are not yet known.
Steps
Partitioning Partitioning is a process of dividing the chip into small blocks. This is done mainly to separate different functional blocks and also to make placement and routing easier. Partitioning can be done in the RTL design phase when the design engineer partitions the entire design into sub-blocks and then proceeds to design each module. These modules are linked together in the main module called the TOP LEVEL module. This kind of partitioning is commonly referred to as Logical Partitioning. The goal of partitioning is to split the circuit such that the number of connections between partitions is minimized.
… excerpt ends here. Continue reading the full article.




