In digital electronics, the power–delay product (PDP) is a figure of merit correlated with the energy efficiency of a logic gate or logic family. Also known as switching energy, it is the product of power consumption P (averaged over a switching event) times the input–output delay or duration of the switching event D. It has the dimension of energy and measures the energy consumed per switching event. In a CMOS circuit the switching energy and thus the PDP for a 0-to-1-to-0 computation cycle is CL·VDD2. Therefore, lowering the supply voltage VDD lowers the PDP. Energy-efficient circuits with a low PDP may also be performing very slowly, thus energy–delay product (EDP), the product of E and D (or P and D2), is sometimes a preferable metric. In CMOS circuits the delay is inversely proportional to the supply voltage VDD and hence EDP is proportional to VDD. Consequently, lowering VDD also benefits EDP.
See also Voltage scaling Switching power
References
Further reading Sah, Chih-Tang (1991-07-11). Fundamentals of Solid-State Electronics (1 ed.). World Scientific. ISBN 978-9-81020637-6. Singh, Brahmadeo Prasad; Singh, Rekha (2008). Electronic Devices and Integrated Circuits. Prentice-Hall Of India Pvt. Limited. ISBN 978-8-12033192-1. Soudris, Dimitrios; Piguet, Christian; Goutis, Costas, eds. (2002-10-31). Designing CMOS Circuits for Low Power. European Low-Power Initiative for Electronic System Design. Springer US. ISBN 978-1-40207234-5. Nebel, Wolfgang; Mermet, Jean, eds. (1997-06-30). Low Power Design in Deep Submicron Electronics. NATO ASI Series. Vol. 337. Kluwer Academic Publishing. ISBN 0-7923-4569-X. ISSN 0168-132X. {{cite book}}: |work= ignored (help)