In the design of integrated circuits, power network design is the analysis and design of on-chip conductor networks that distribute electrical power on a chip. Issues in the design include voltage drop, current density in conductors, the physical size of conductors in a metal layer of a chip, and reduction of undesired noise conducted through the distribution network. Design methods and software tools for layout of power networks may require iteration to produce a desirable design. Various methods are used to model current demands on the chip to reduce the complexity of simulation calculations. On-chip networks may serve millions of device. High-speed switching constrains design choices in the power network. Simulations are used to verify proper performance under worst-case conditions.
Function The power distribution network distributes power and ground voltages from pad locations to all devices in a design. Shrinking device dimensions, faster switching frequencies and increasing power consumption in deep sub-micrometer technologies cause large switching currents to flow in the power and ground networks which degrade performance and reliability. A robust power distribution network is essential to ensure reliable operation of circuits on a chip. Power supply integrity verification is a critical concern in high-performance designs.
Design considerations Due to the resistance of the interconnects constituting the network, there is a voltage drop across the network, commonly referred to as the IR-drop. The package supplies currents to the pads of the power grid either by means of package leads in wire-bond chips or through C4 bump arrays in flip chip technology. Although the resistance of package leads is quite small, their inductance can be significant, causing a voltage drop at the pad locations due to the time varying current drawn by the devices on die. This voltage drop is referred to as the di/dt-drop. Therefore, the voltage seen at the devices is the supply voltage minus the IR-drop and di/dt-drop. Excessive voltage drops in the power grid reduce switching speeds and noise margins of circuits, and inject noise which might lead to functional failures. High average current densities lead to undesirable wearing out of metal wires due to electromigration (EM). Therefore, the challenge in the design of a power distribution network is in achieving excellent voltage regulation at the consumption points notwithstanding the wide fluctuations in power demand across the chip, and to build such a network using minimum area of the metal layers while supporting a long chip lifetime. These issues are prominent in high performance chips such as microprocessors, since large amounts of power have to be distributed through a hierarchy of many metal layers. A robust power distribution network is vital in meeting performance guarantees and ensuring reliable operation. Capacitance between power and ground distribution networks, referred to as decoupling capacitors or decaps, acts as local charge storage and is helpful in mitigating the voltage drop at supply points. Parasitic capacitance between metal wires of supply lines, device capacitance of the non-switching devices, and capacitance between N-well and substrate, occur as implicit decoupling capacitance in a power distribution network. Unfortunately, this implicit decoupling capacitance is sometimes not enough to constrain the voltage drop within safe bounds and designers often have to add intentional explicit decoupling capacitance structures on the die at strategic locations. These explicitly added decoupling capacitances are not free and increase the area and leakage power consumption of the chip. Parasitic interconnect resistance, decoupling capacitance and package/interconnect inductance form a complex RLC circuit which has its own resonance frequencies. If these frequencies lie close to the operating frequency of the design, large voltage drops can develop in the grid. The crux of the problem in designing a power grid is design closure. There are many unknowns until the very end of the design cycle, but decisions about the structure, size and layout of the power grid have to be made at very early stages when a large part of the chip design has not even begun. The most accurate analysis is obtained by post-layout verification of the power grid when the entire chip design is complete and detailed information about the parasitics of the power and ground lines and the currents drawn by the transistors are known. However, power grid problems revealed at this stage are usually very difficult or expensive to fix, so modern analysis tools help to design an initial power grid and refine it progressively at various design stages. Due to the growth in power consumption and switching speeds of modern high performance microprocessors, the di/dt effects are becoming a growing concern in high speed designs. Clock gating, which is a preferred scheme for power management of high performance designs, can cause rapid surges in current demands of macro-blocks and increase di/dt effects. Designers rely on the on-chip parasitic capacitances and intentionally added decoupling capacitors to counteract the di/dt variations in the voltage. But it is necessary to model accurately the inductance and capacitance of the package and chip and analyze the grid with such models, as otherwise the amount of decoupling to be added might be underestimated or overestimated. Also it is necessary to maintain the efficiency of the analysis even when including these detailed models.
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