Quilt Packaging (QP) is an integrated circuit packaging and chip-to-chip interconnect packaging technology that utilizes "nodule" structures that extend out horizontally from the edges of microchips to make chip-to-chip interconnections. QP nodules are created as an integral part of a microchip using standard back end of the line techniques in semiconductor device fabrication. Solder is then electroplated on top of the nodules to enable the chip to chip interconnection with sub-micron alignment accuracy. Small high yielding "chiplets" made from any semiconductor material (silicon, gallium arsenide, silicon carbide, gallium nitride, etc.), can be "quilted" together to create larger multi-function meta-chip. Thus, QP technology can integrate multiple chips with dissimilar technologies or substrate materials in planar, 2.5D and 3D configurations.
RF Analog Performance Multiple measured insertion loss on QP interconnects have been conducted on quilted chipsets with sets of homogeneous and heterogeneous semiconductor materials. Radio frequency S-parameter measurements were made from DC to 220 GHz. QP interconnects have demonstrated less than 0.1 dB insertion loss from DC to 100 GHz between silicon and silicon chips, and less than 0.8 dB insertion loss up to 220 GHz between Silicon and Gallium Arsenide.
Digital Performance QP interconnects have a achieved 12 gigabit/sec (Gbps) bit-rate throughput with no distortion with 10 μm nodules on a 10 μm pitch on the edge of the chip.
Optics/Photonics Preliminary optical coupling loss simulations and measurements indicate that inter-chip coupling loss is < 6 dB for a gap of less than 4 μm. Loss rapidly improves as the gap approaches zero, which is achievable with Quilt Packaging assembly tolerances.
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