computer science

RISC-V

RISC-V is a computer science topic covered in the lgStudy science library. This page brings together a partial reference excerpt, illustrations, worked examples, real-world applications and a short study plan, so you can understand RISC-V rather than just read about it. In short: RISC-V (pronounced "risk-five") is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties.

RISC-V — illustration

Key takeaways

RISC-V belongs to computer science; place it in that map before memorising details.
Learn the definition first, then one example that makes the definition concrete.
Connect RISC-V to a quantity you can measure, compute or draw — that is where exam questions come from.
Reproduce the core statement of RISC-V from memory before moving on to harder problems.

Reference excerpt

RISC-V (pronounced "risk-five") is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981. In 2015, development and maintenance of the standard was transferred to RISC-V International, a non-profit organization based in Switzerland with more than 4,500 members as of 2025. RISC-V is a popular architecture for microcontrollers and embedded systems, with development of higher-performance implementations targeting mobile, desktop, and server markets ongoing. The ISA is supported by several major Linux distributions, and companies such as SiFive, Andes Technology, SpacemiT, Synopsys, Alibaba (DAMO Academy), StarFive, Espressif Systems, and Raspberry Pi offer commercial systems on a chip (SoCs) and microcontrollers (MCUs) that incorporate one or more RISC-V compatible processor cores.

History The term RISC dates from about 1980. Before then, there was some knowledge (see John Cocke) that simpler computers can be effective, but the design principles were not widely described. Simple, effective computers have always been of academic interest, and resulted in the RISC instruction set DLX for the first edition of Computer Architecture: A Quantitative Approach in 1990 of which David Patterson was a co-author, and he later participated in the RISC-V origination. DLX was intended for educational use; academics and hobbyists implemented it using field-programmable gate arrays (FPGA), but it was never truly intended for commercial deployment. Krste Asanović at the University of California, Berkeley, had a research requirement for an open-source CPU core, and in 2010, he decided to develop and publish his own, in a "short, three-month project over the summer" with several of his graduate students. Several established open-source alternatives were available, but Asanović chose not to use them. ARM and SuperH CPUs (versions 2 and earlier) had public-domain instruction sets with VHDL implementation files, while complete OpenRISC, OpenPOWER, and OpenSPARC / LEON cores were also available either as VHDL files or from various vendors. All of these existing options were supported by the GNU Compiler Collection (GCC), a popular free-software compiler, and had Linux kernel support. The plan was to aid both academic and industrial users. David Patterson at Berkeley joined the collaboration as he was the originator of the Berkeley RISC, and the RISC-V is the eponymous fifth generation of his long series of cooperative RISC-based research projects at the University of California, Berkeley (RISC-I and RISC-II published in 1981 by Patterson, who refers to the SOAR architecture from 1984 as "RISC-III" and the SPUR architecture from 1988 as "RISC-IV"). At this stage, students provided initial software, simulations, and CPU designs.

The RISC-V authors and their institution originally sourced the ISA documents and several CPU designs under BSD licenses, which allow derivative works—such as RISC-V chip designs—to be either open and free, or closed and proprietary. The ISA specification itself (i.e., the encoding of the instruction set) was published in 2011 as open source, with all rights reserved. The actual technical report (an expression of the specification) was later placed under the license Creative Commons - Attribution 4.0 to permit enhancement by external contributors through the RISC-V Foundation, and later RISC-V International. A full history of RISC-V has been published on the RISC-V International website.

Foundations Commercial users require an ISA to be stable before they can use it in a product that may last many years. To address this issue, the RISC-V Foundation was formed in 2015 to own, maintain, and publish intellectual property related to RISC-V's definition. The original authors and owners have surrendered their rights to the foundation. The foundation was led by CEO Calista Redmond, who took on the role in 2019 after leading open infrastructure projects at IBM. In 2024 she resigned as CEO. The founding members of RISC-V were: Andes Technology, Antmicro, Bluespec, Ceva, Codasip, Cortus, Esperanto Technologies, Espressif Systems, ETH Zurich, Google, IBM, ICT, IIT Madras, Lattice Semiconductor, LowRISC, Microchip Technology, the MIT Computer Science and Artificial Intelligence Laboratory, Qualcomm, Rambus, Rumble Development, SiFive, Syntacore and Technolution. In November 2019, the RISC-V Foundation announced that it would relocate to Switzerland, citing concerns over U.S. trade regulations. As of March 2020, the organization was named RISC-V International, a Swiss nonprofit business association. As of 2019, RISC-V International freely publishes the documents defining RISC-V and permits unrestricted use of the ISA for design of software and hardware. However, only members of RISC-V International can vote to approve changes, and only member organizations use the trademarked compatibility logo. The Linux Foundation Europe started the RISC-V Software Ecosystem (RISE) initiative on May 31, 2023. The goal of RISE is to increase the availability of software for high-performance and power-efficient RISC-V processors running high-level operating systems for a range of market segments by bringing together a large number of hardware and software vendors. Red Hat, Samsung, Qualcomm, Nvidia, MediaTek, Intel, and Google are among the initial members. In early May 2026, RISC-V International launched the RISC-V Ratified Specifications Library, a centralized documentation hub consolidating all ratified RISC-V specifications—including the ISA, profiles, debug, trace, ABI, and platform/firmware interfaces—into a single location. Previously, RISC-V documentation had been spread across numerous GitHub repositories, draft pages, mailing lists, and independently maintained sources, which RISC-V International said had made it difficult for engineers in ASIC design, verification, firmware, and toolchain development to locate the correct specification version.

Awards 2017: The Linley Group's Analyst's Choice Award for Best Technology (for the instruction set)

Rationale

… excerpt ends here. Continue reading the full article.

Illustrations

Worked examples

Example 1 — a first encounter with RISC-V

Start with the simplest possible case. Write down what RISC-V claims or describes in one sentence, then invent the smallest concrete situation in which that sentence is true. In computer science, the smallest case is usually a single object, a single equation or a single measurement. Check that every symbol or term in your sentence has a meaning in that case.

Example 2 — changing one variable

Take the situation from Example 1 and change exactly one quantity: double it, halve it, or set it to zero. Predict what should happen to RISC-V before you calculate. Comparing your prediction with the result is the fastest way to find out whether you understand the idea or only the words.

Example 3 — an exam-style question

Typical questions about RISC-V ask you to (a) state it precisely, (b) apply it to given data, and (c) explain a limitation. Practise writing all three answers in under five minutes; the third part is what separates a full-mark answer from an average one.

Applications of RISC-V

In research: RISC-V appears in computer science research whenever the underlying quantities have to be modelled precisely. Papers usually cite it as a starting assumption and then explore where it breaks down.
In technology and industry: Engineering practice reuses RISC-V in design rules, simulations and safety margins. Knowing the idea lets you read a specification sheet and understand why the numbers look the way they do.
In the classroom: RISC-V is common in secondary-school and first-year university syllabi. It links to neighbouring topics 64-bit computers, Computer-related introductions in 2010, Instruction set architectures, so understanding it makes those chapters shorter.
In everyday life: Look for RISC-V outside the textbook — in sport, cooking, traffic, electronics or the sky above you. An example you found yourself is remembered far longer than one you were given.

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How to study RISC-V in 20 minutes

Read the reference excerpt below once, without taking notes.
Close the page and write down what RISC-V means in your own words.
Compare your version with the excerpt and mark what you missed.
Work through the three examples above with pen and paper.
Explain RISC-V out loud to somebody else — or to Teacher Smith in the lgStudy chat.

Frequently asked questions

What is RISC-V in simple terms?

Why does RISC-V matter?

Because it connects several computer science ideas at once: it gives you a definition you can apply, a quantity you can calculate, and a way to check whether a result is plausible.

How should I study RISC-V?

Read the excerpt, restate it from memory, then work through the examples and applications listed on this page. The five-step study plan above takes about twenty minutes.

What does this page cover?

It gives you a compact reference excerpt plus original lgStudy explanations, examples, applications and study material on RISC-V.