A register file is an array of addressable registers which has two or more ports that allow concurrent reading and writing of registers in the array. Reading is nondestructive, meaning that the act of reading does not alter the stored data. Each port is either a write port or a read port, with input and output signals relevant to the port function. All ports have address inputs that specify the register to be accessed. Write ports also have data inputs that specify the value to be written to the register, and a write enable input that allows the data to be written. Read ports have data outputs that convey the register's output value. Register files are used in a variety of applications, including as processor registers in central processing units (CPUs), as data memory in FIFOs, and in hardware accelerators.
Typical architecture
In central processing units (CPUs) The instruction set architecture of a CPU will almost always define a set of registers which are used to stage data between memory and the functional units on the chip. The register file is part of the architecture and visible to the programmer, as opposed to the concept of transparent caches. In simpler CPUs, these architectural registers correspond one-for-one to the entries in a physical register file (PRF) within the CPU. More complicated CPUs use register renaming, so that the mapping of which physical entry stores a particular architectural register changes dynamically during execution. Register banking is the method of using a single name to access multiple different physical registers depending on the operating mode.
Register-bank switching Register files may be clubbed together as register banks. A processor may have more than one register bank. ARM processors have both banked and unbanked registers. While all modes always share the same physical registers for the first eight general-purpose registers (GPR), R0 to R7, the physical register which the banked registers, R8 to R14, point to depends on the operating mode the processor is in. Notably, Fast Interrupt Request (FIQ) mode has its own bank of registers for R8 to R12, with the architecture also providing a private stack pointer (R13) for every interrupt mode. x86 processors use context switching and fast interrupts for switching between instruction, decoder, GPRs and register files, if there is more than one, before the instruction is issued, but this only exists on processors that support superscalar execution. However, context switching is a totally different mechanism to ARM's register bank within the registers. The MODCOMP and the later 8051-compatible processors use bits in the program status word to select the currently active register bank.
Physical implementation
The usual layout convention is that a simple array is read out vertically. That is, a single word line, which runs horizontally, causes a row of bit cells to put their data on bit lines, which run vertically. Sense amps, which convert low-swing read bitlines into full-swing logic levels, are usually at the bottom (by convention). Larger register files are then sometimes constructed by tiling mirrored and rotated simple arrays. Register files have one word line per entry per port, one bit line per bit of width per read port, and two bit lines per bit of width per write port. Each bit cell also has a Vdd and Vss. Therefore, the wire pitch area increases as the square of the number of ports, and the transistor area increases linearly. At some point, it may be smaller and/or faster to have multiple redundant register files, with smaller numbers of read ports, rather than a single register file with all the read ports. The MIPS R8000's integer unit, for example, had a 9 read 4 write port 32 entry 64-bit register file implemented in a 0.7 μm process, which could be seen when looking at the chip from arm's length. Two popular approaches to dividing registers into multiple register files are the distributed register file configuration and the partitioned register file configuration. In principle, any operation that could be done with a 64-bit-wide register file with many read and write ports could be done with a single 8-bit-wide register file with a single read port and a single write port. However, the bit-level parallelism of wide register files with many ports allows them to run much faster and thus, they can do operations in a single cycle that would take many cycles with fewer ports or a narrower bit width or both. The width in bits of the register file is usually the number of bits in the processor word size. Occasionally it is slightly wider in order to attach "extra" bits to each register, such as the poison bit. If the width of the data word is different than the width of an address—or in some cases, such as the 68000, even when they are the same width—the address registers are in a separate register file than the data registers.
Decoder The decoder is often broken into pre-decoder and decoder proper. The decoder is a series of AND gates that drive word lines. There is one decoder per read or write port. If the array has four read and two write ports, for example, it has 6 word lines per bit cell in the array, and six AND gates per row in the decoder. Note that the decoder has to be pitch matched to the array, which forces those AND gates to be wide and short.
Array
The basic scheme for a bit cell:
State is stored in pair of inverters. Data is read out by NMOS transistor to a bit line. Data is written by shorting one side or the other to ground through a two-NMOS stack. So: read ports take one transistor per bit cell, write ports take four. Many optimizations are possible:
… excerpt ends here. Continue reading the full article.
