In computer architecture, register renaming is a technique that abstracts logical registers from physical registers. Every logical register has a set of physical registers associated with it. When a machine language instruction refers to a particular logical register, the processor transposes this name to one specific physical register on the fly. The physical registers are opaque and cannot be referenced directly but only via the canonical names. This technique is used to eliminate false data dependencies arising from the reuse of registers by successive instructions that do not have any real data dependencies between them. The elimination of these false data dependencies reveals more instruction-level parallelism in an instruction stream, which can be exploited by various and complementary techniques such as superscalar and out-of-order execution for better performance.
Problem approach Programs are composed of instructions which operate on values. The instructions must name these values in order to distinguish them from one another. A typical instruction might say: add x {\displaystyle x} and y {\displaystyle y} and put the result in z {\displaystyle z} . In this instruction, x {\displaystyle x} , y {\displaystyle y} and z {\displaystyle z} are the names of storage locations. It is common for the values being manipulated to be used several times in succession. Register machines take advantage of this by introducing a number of processor registers, which are high-speed memory locations that hold these values. Since register access is typically much faster than accessing memory, high-performance code and processors try to operate on registers when possible. The collection of registers in a particular design is known as its register file. Individual registers in the file are referred to by number in the machine code. Encoding a number in the machine code requires several bits. For instance, in the Zilog Z80 there were eight general-purpose registers in the file. To select one of eight values requires three bits, as 23 = 8. More architectural (logical) registers of the same width and type can result in better performance, as more temporary values can be held in registers and thus avoid the expensive operations of saving or loading from memory. Similarly, wider registers that can hold more data can also improve performance, if the workload can make use of that. Generally, more modern processors and those with larger instruction words will use more registers when possible. For example, the IA-32 instruction set architecture has 8 general purpose registers, x86-64 has 16, many RISCs have 32, and IA-64 has 128. The advantages of a larger register file are offset by the need to use more bits to encode the register number. For instance, in a system using 32-bit instructions, you might wish to have three registers, such that you can perform operations of the type z {\displaystyle z} = x + y {\displaystyle x+y} . If the register file contains 32 entries, each one of the references will require 5 bits, and the set of three registers thus takes up 15 bits, leaving 17 to encode the operation and other information. Expanding the register file to 64 entries would require 6 bits, a total of 18 bits. While this may result in faster performance, it also means there are fewer bits left over for encoding the instruction. This leads to an effort to balance the size of the file with the number of possible instructions.
Out-of-order Processors in early computers often worked lock-step with their main memory, which reduced the advantages of large register files. A common design note from the minicomputer market of the 1960s was to have the registers be physically implemented in main memory, in which case the performance advantage was simply that the instruction could directly refer to the location rather than having to use a second byte or two to specify a complete memory address. This made the instructions smaller, and thus faster to read. This sort of design, which maximized performance by carefully tuning the instruction set for minimal size, was common until the 1980s. An example of this approach is the MOS 6502, which had only a single register, in which case it is referred to as the accumulator, and a special "zero page" addressing mode for the first 256 bytes of memory. Placing code and data in the zero page meant the instruction was only two bytes long instead of three, greatly improving performance through avoided reads, providing similar benefits to having more registers. The widespread introduction of dynamic RAM in the 1970s changed this approach. Over time, the performance of the central processing units (CPUs) increased relative to the memory they were attached to, it was no longer reasonable to use main memory as registers. This led to increasingly large register files, internal to the CPU, to avoid referring to memory wherever possible. However, it is not possible to avoid accessing memory entirely in practice, and as the speed difference grew, every such access became more and more expensive in terms of the number of instructions that might be performed had the value been in a register. Different instructions may take different amounts of time; for example, a processor may be able to execute hundreds of register-to-register instructions while a single load from the main memory is in progress. A key advance in improving performance is to allow those fast instructions to be performed while the others are waiting for data. This means the instructions are no longer completed in the order they are specified in the machine code, they are instead performed out-of-order. Consider this piece of code running on an out-of-order CPU:
The instructions in the final three lines are independent of the first three instructions, but the processor cannot finish r1 ≔ m[2048] until the preceding m[1032] ≔ r1 is complete, as doing so would add four to the value of 1024, not 2048. If another register is available, this restriction can be eliminated by choosing different registers for the first three and the second three instructions:
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