Reliability of a semiconductor device is the ability of the device to perform its intended function during the life of the device in the field. There are multiple considerations that need to be accounted for when developing reliable semiconductor devices:
Semiconductor devices are very sensitive to impurities and particles. Therefore, to manufacture these devices it is necessary to manage many processes while accurately controlling the level of impurities and particles. The finished product quality depends upon the many layered relationship of each interacting substance in the semiconductor, including metallization, chip material (list of semiconductor materials) and package. The problems of micro-processes, and thin films and must be fully understood as they apply to metallization and wire bonding. It is also necessary to analyze surface phenomena from the aspect of thin films. Due to the rapid advances in technology, many new devices are developed using new materials and processes, and design calendar time is limited due to non-recurring engineering constraints, plus time to market concerns. Consequently, it is not possible to base new designs on the reliability of existing devices. To achieve economy of scale, semiconductor products are manufactured in high volume. Furthermore, repair of finished semiconductor products is impractical. Therefore, incorporation of reliability at the design stage and reduction of variation in the production stage have become essential. Reliability of semiconductor devices may depend on assembly, use, environmental, and cooling conditions. Stress factors affecting device reliability include gas, dust, contamination, voltage, current density, temperature, humidity, mechanical stress, vibration, shock, radiation, pressure, and intensity of magnetic and electrical fields. Design factors affecting semiconductor reliability include: voltage, power, and current derating; metastability; logic timing margins (logic simulation); timing analysis; temperature derating; and process control.
Methods of improvement Reliability of semiconductors is kept high through several methods. Cleanrooms control impurities, process control controls processing, and burn-in (short term operation at extremes) and probe and test reduce escapes. Probe (wafer prober) tests the semiconductor die, prior to packaging, via micro-probes connected to test equipment. Final test tests the packaged device, often pre-, and post burn-in for a set of parameters that assure operation. Process and design weaknesses are identified by applying a set of stress tests in the qualification phase of the semiconductors before their market introduction e. g. according to the AEC Q100 and Q101 stress qualifications. Parts Average Testing is a statistical method for recognizing and quarantining semiconductor die that have a higher probability of reliability failures. This technique identifies characteristics that are within specification but outside of a normal distribution for that population as at-risk outliers not suitable for high reliability applications. Tester-based Parts Average Testing varieties include Parametric Parts Average Testing (P-PAT) and Geographical Parts Average Testing (G-PAT), among others. Inline Parts Average Testing (I-PAT) uses data from production process control inspection and metrology to perform the outlier recognition function. Bond strength measurement is performed in two basic types: pull testing and shear testing. Both can be done destructively, which is more common, or non destructively. Non destructive tests are normally used when extreme reliability is required such as in military or aerospace applications.
Failure mechanisms Failure mechanisms of electronic semiconductor devices fall in the following categories
Material-interaction-induced mechanisms. Stress-induced mechanisms. Mechanically induced failure mechanisms. Environmentally induced failure mechanisms.
Material-interaction-induced mechanisms Field-effect transistor gate-metal sinking Ohmic contact degradation Channel degradation Surface-state effects Package molding contamination—impurities in packaging compounds cause electrical failure
Stress-induced failure mechanisms Electromigration – electrically induced movement of the materials in the chip Burnout – localized overstress Charge trapping Hot electron trapping – due to overdrive in power RF circuits Hot-carrier injection Bias temperature instability Electrical stress – electrostatic discharge, high electro-magnetic fields (HIRF), latch-up overvoltage, overcurrent
Mechanically induced failure mechanisms Die fracture – due to mis-match of thermal expansion coefficients Die-attach voids – manufacturing defect—screenable with scanning acoustic microscopy. Solder joint failure by creep fatigue or intermetallics cracks. Die-pad/molding compound delamination due to thermal cycling
Environmentally induced failure mechanisms Humidity effects – moisture absorption by the package and circuit Hydrogen effects – hydrogen-induced breakdown of portions of the circuit (metal) Other temperature effects—accelerated aging, increased electro-migration with temperature, increased burn-out
Failure prediction Depending on the failure mechanism, physics of failure techniques can be utilised to predict the failure of the semiconductor, such as the Coffin-Manson law and the Paris' law. However, data-driven techniques often complement these approaches to account for uncertainty caused by simultaneous failure mechanisms for example.
See also Transistor aging Failure analysis Cleanroom Burn-in List of materials-testing resources List of materials analysis methods
References
… excerpt ends here. Continue reading the full article.
