Shakti (stylized as SHAKTI) is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT Madras to develop the first indigenous industrial-grade processor. The aims of the Shakti initiative include building an open source production-grade processor, complete systems on a chip, microprocessor development boards, and a Shakti-based software platform. The main focus of the team is computer architecture research to develop SoCs, which are competitive with commercial offerings in the market in area, power, and performance. The source code for Shakti is open-sourced under the Modified BSD License. V. Kamakoti carried out the SHAKTI Microprocessor Project, at Prathap Subrahmanyam Centre for Digital Intelligence and Secure Hardware Architecture (Department of Computer Science & Engineering, IIT Madras). The Ministry of Electronics and Information Technology supports it through its Digital India RISC-V initiative.
Processors Shakti processors are based on the RISC-V instruction set architecture (ISA). The processors are designed to have either 22 nm process fin field-effect transistor (FinFET) or 180 nm process complementary metal–oxide–semiconductor (CMOS) technology nodes depending on the manufacturing semiconductor fabrication plant (foundry). Shakti plans a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors". The E and C-classes core are for the Internet of things (IoT), embedded system, and desktop computer markets. The processor design is free of any royalty and is open-source licensed under the modified BSD License. E-class and C-class cores are both implemented in Bluespec SystemVerilog (BSV) language, a Haskell dialect. The Shakti project aims to build 6 variants of processors based on the RISC-V ISA.
Base classes of processors
E-class The E-class are 32- and 64-bit microcontrollers able to support all extensions of the RISC-V ISA, for low-power and low computer applications. The E-class is an in-order 3 stage pipeline having an operational frequency of less than 200 MHz on silicon. It is positioned against ARM's M-class (Cortex-M series) cores. It can run real-time operating systems like FreeRTOS, Zephyr, and eChronos. Market segments of E-class processor support smart cards, IoT devices, motor controls, and robotic platforms. E-arty35T is a SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 general-purpose input/output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a platform level interrupt controller (PLIC), a Counter, 2 Serial Peripheral Interface (SPI), 2 universal asynchronous receiver-transmitter (UART), 1 Inter-Integrated Circuit (I²C), 6 pulse-width modulator (PWM) and an inbuilt Xilinx analog-to-digital converter (X-ADC).
C-class The C-class is a 64-bit controller class of processor, for mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and the capability to run operating systems like Linux and Sel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It is for mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. The application domain of this class ranges from embedded systems, motor-control, IoT, storage, industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc. C-arty100T is a SoC built around the C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I²C). It is for mid-range application workloads with a very low power use and support for optional memory protection.
I-class The I-class is a 64-bit processor for the compute, mobile, storage, and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep instruction pipelining stages. The operational clock frequency of this processor is 1.5-2.5 GHz. As of April 2020, the team was working on implementing atomics, memory dependence prediction, instruction window/scheduler optimizations, implementation of some functional units, performance analysis/projections, optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor.
Multicore processors
M-class A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are for general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance goals.
S-class The S-Class is a 64-bit superscalar, multi-threaded variant for desktop and enterprise server uses. Its supports 2–16 cores with a clock frequency of about 1.2–3 GHz.
H-class The H-class is a 64-bit processor for highly parallel enterprise, HPC, and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core.
Experimental processors These are experimental/research projects which focus on developing a high security and fault tolerant processor.
T-class The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks.
F-class The F-class is a fault-tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.
Tapeouts Two C-class processors (codenamed RIMO and Risecreek) and one E-class processor (Moushik) have been taped-out so far.
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