In semiconductor electronics fabrication technology, a self-aligned gate is a transistor manufacturing approach whereby the gate electrode of a MOSFET (metal–oxide–semiconductor field-effect transistor) is used as a mask for the doping of the source and drain regions. This technique ensures that the gate is naturally and precisely aligned to the edges of the source and drain. The use of self-aligned gates in MOS transistors is one of the key innovations that led to the large increase in computing power in the 1970s. Self-aligned gates are still used in most modern integrated circuit processes.
Introduction
IC construction
Integrated circuits (ICs, or "chips") are produced in a multi-step process that builds up multiple layers on the surface of a disk of silicon known as a "wafer". Each layer is patterned by coating the wafer in photoresist and then exposing it to ultraviolet light being shone through a stencil-like "mask". Depending on the process, the photoresist that was exposed to light either hardens or softens, and in either case, the softer parts are then washed away. The result is a microscopic pattern on the surface of the wafer where a portion of the top layer is exposed while the rest is protected under the remaining photoresist. The wafer is then exposed to a variety of processes that add or remove materials from the portions of the wafer that are unprotected by the photoresist. In one common process, the wafer is heated to around 1000 °C and then exposed to a gas containing a doping material (commonly boron or phosphorus) that changes the electrical properties of the silicon. This allows the silicon to become an electron donor, electron receptor, or near-insulator depending on the type and/or amount of the dopant. In a typical IC this process is used to produce the individual transistors that make up the key elements of an IC. In the MOSFET, the three parts of a transistor are the source, the drain, and the gate (see diagram). The "field effect" in the name refers to changes to the conductivity that occur when a voltage is applied to the gate. The key point is that this electric field can cause the "channel" region separating the source and drain to become the same type as the source-drain, thus turning the transistor "on". Because no current flows from the gate to the drain, the switching energy of a FET is very small compared to earlier bipolar junction transistor types where the gate (or base as it was known) was in-line with the current.
Older methodology In early MOSFET fabrication methodologies, the gate was made of aluminum which melts at 660 °C, so it had to be deposited as one of the last steps in the process after all the doping stages had been completed at around 1000 °C. The wafer as a whole is first chosen to have a particular electrical quality as biased either positive, or "p", or negative, "n". In the illustration the base material is "p", so the channels will be made "n", which is known as n-channel or nMOS. A mask is then used to produce areas where the negative "n" sections of the transistors will be placed. The wafer is then heated to around 1000 °C, and exposed to a doping gas that diffuses into the surface of the wafer to produce the "n" sections. A thin layer of insulator material (silicon dioxide) is then grown on top of the wafer. Finally, the gate is patterned on top of the insulating layer in a new photo-lithographic operation. To ensure the gate actually overlaps the underlying source and drain, the gate material has to be wider than the gap between the n sections, typically as much as three times. This wastes space and creates extra capacitance between the gate and the source-drain. This parasitic capacitance requires that the entire chip be driven at high power levels to ensure clean switching which is inefficient. Additionally, the variation in the misalignment of the gate to the underlying source-drain means that there is high chip-to-chip variability even when they are working properly.
Self-alignment
The self-aligned gate developed in several steps to its present form. Key to the advance was the discovery that heavily doped poly-silicon was conductive enough to replace aluminum. This meant the gate layer could be created at any stage in the multi-step fabrication process. In the self-aligned process, the key gate-insulating layer is formed near the beginning of the process. Then the gate is deposited and patterned on top. Then the source-drains are doped (for poly-silicon the gates are doped simultaneously). The source-drain pattern thus represents only the outside edges of the source and drain, the inside edge of those sections being masked by the gate itself. As a result, the source and drain "self-align" to the gate. Since they are always perfectly positioned, there is no need to make the gate wider than desired, and the parasitic capacitance is greatly reduced. Alignment time and chip-to-chip variability are likewise reduced. After early experimentation with different gate materials using aluminum, molybdenum and amorphous silicon, the semiconductor industry almost universally adopted self-aligned gates made with polycrystalline silicon (poly-silicon), the so-called silicon-gate technology (SGT) or "self-aligned silicon-gate" technology, which had many additional benefits over the reduction of parasitic capacitances. One important feature of SGT was that the transistor was entirely buried under top quality thermal oxide (one of the best insulators known), making it possible to create new device types, not feasible with conventional technology or with self-aligned gates made with other materials. Particularly important are charge-coupled devices (CCD), used for image sensors, and non-volatile memory devices using floating silicon-gate structures. These devices dramatically enlarged the range of functionality that could be achieved with solid state electronics. Certain innovations were required in order to make self-aligned gates:
a new process that would create the gates; a switch from amorphous silicon to polycrystalline silicon (because amorphous silicon would break where it passed over "steps" in the oxide insulating surface); a photolithography method for etching polycrystalline silicon; a method to reduce the impurities present in silicon. Prior to these innovations, self-aligned gates had been demonstrated on metal-gate devices, but their real impact was on silicon-gate devices.
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