A successive-approximation ADC (or SAR ADC) is a type of analog-to-digital converter (ADC) that digitizes each sample from a continuous analog waveform using a binary search through all possible quantization levels.
Structure
A successive-approximation analog-to-digital converter contains several component subcircuits:
An analog voltage comparator that compares Vin to the output of a digital-to-analog converter (DAC). A successive-approximation register that is updated by the results of the comparator to provide the DAC with a digital code whose accuracy increases with each successive iteration. A DAC that supplies the comparator with an analog voltage relative to the reference voltage Vref (which corresponds to the full-scale range of the ADC) and proportional to the digital code of the SAR. In many implementations, a sample-and-hold circuit is used to acquire the input voltage prior to starting a conversion. This holds the acquired voltage steady while a conversion is in progress. It is required if Vin can change rapidly enough to cause conversion errors, and is inherently an integral part of some types of ADCs (e.g., charge-redistribution ADC).
Algorithm Drummer and Ray described the algorithm as applied to a digital voltmeter. This paper predates ADC integrated circuits but describes the binary search decision-making. The successive-approximation register is initialized with 1 in the most significant bit (MSB) and zeroes in the lower bits. The register's code is fed into the DAC, which provides an analog equivalent of its digital code (initially 1/2Vref) to the comparator for comparison with the sampled input voltage. If this analog voltage exceeds Vin, then the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1, and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximated output of the sampled input voltage.
The algorithm's objective for the nth iteration is to approximately digitize the input voltage to an accuracy of 1⁄2n relative to the reference voltage. To show this mathematically, the normalized input voltage is represented as x in [−1, 1] by letting Vin = xVref. The algorithm starts with an initial approximation of x0 = 0 and during each iteration i produces the following approximation:ith approximation: xi = xi−1 − sgn(xi−1 − x)/2iwhere the binary signum function sgn mathematically represents the comparison of the previous iteration's approximation xi-1 with the normalized input voltage x: s g n ( x i − 1 − x ) = { + 1 if x i − 1 ≥ x , − 1 if x i − 1 < x . {\displaystyle sgn(x_{i-1}-x)={\begin{cases}+1&{\text{if }}x_{i-1}\geq x,\\-1&{\text{if }}x_{i-1}<x.\end{cases}}} It follows using mathematical induction that the approximation of the nth iteration theoretically has a bounded accuracy of: |xn − x| ≤ 1/2n.
Examples
Example 9-bit ADC The steps to converting an analog input to 9-bit digital, using successive-approximation, are shown here for all voltages from 5 V to 0 V in 0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is also 5 V, all bits are set. As the voltage is decreased to 4.9 V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5 V. The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625. All of these add up to 4.990234375, meaning binary 111111111, or one LSB less than 5. When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5 V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the result, a binary number representing the analog input, is found.
Example 4-bit ADC The working of a 4-bit successive-approximation ADC is illustrated below. The MSB is initially set to 1, whereas the remaining digits are set to zero. If the input voltage is lower than the value stored in the register, on the next clock cycle, the register changes its value to that illustrated in the figure by following the green line. If the input voltage is higher, then on the next clock cycle, the register changes its value to that illustrated in the figure by following the red line. The simplified structure of this type of ADC that acts on 2n volts range can be expressed as an algorithm:
Initialize register with MSB set to 1 and all other values set to zero. In the nth clock cycle, if voltage is higher than digital equivalent voltage of the number in register, the (n+1)th digit from the left is set to 1. If the voltage were lower than digital equivalent voltage, then nth digit from left is set to zero and the next digit is set to 1. To perform a conversion, an N-bit ADC requires N such clock cycles, excluding the initial state.
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