SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems. At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the register file was smaller and instructions were generally two-operand format. However, for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency. Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the machine code to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a compressed instruction set and is also used by other companies, the most notable examples being ARM for its Thumb instruction set, along with RISC-V for its compressed extensions. In 2015, many of the original patents for the SuperH architecture expired and the SH-2 CPU was reimplemented as open source hardware under the name J2.
History
SH-1 and SH-2
The SuperH processor core family was first developed by Hitachi in the early 1990s. The design concept was for a single instruction set (ISA) that would be upward compatible across a series of CPU cores. In the past, this sort of design problem would have been solved using microcode, with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models. One of the key realizations during the development of the RISC concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported MUL, DMULS and DMULU, whereas the SH-1 would cause a trap if these were encountered. The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions. The SH-1 and the SH-2 were used in the Sega Saturn, Sega 32X and Capcom CPS-3. The ISA uses 16-bit instructions for better code density than 32-bit instructions, which was important at the time due to the high cost of main memory and the implementation cost of cache. As of 2023, code density is still important for small embedded systems and massively multicore processors. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the original SuperH ISA, there were only 16 general registers, requiring four bits for the source and another four for the destination; however some instructions have an implied R0, R15, or a system register as an extra operand. The instruction opcode is four, eight, twelve, or sixteen bits long, and the remaining four-bit fields are used for register or immediate operands in various ways: there are twelve classes of instructions, for a total of 142 instructions in SH-2. Delayed branches are introduced for both SH-1 and SH-2. Unconditional branch instructions have one delay slot.
SH-3 A few years later, the SH-3 core was added to the family; new features included another interrupt concept, a memory management unit (MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68. The SH-3 was bi-endian, running in either big-endian or little-endian byte ordering. The SH-3 core also added a DSP extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core. It was used in Microsoft's Pocket PC cellphone line. Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.
SH-4 In 1997, Hitachi and STMicroelectronics (STM) started collaborating on the design of the SH-4 for the Dreamcast. SH-4 featured superscalar (2-way) instruction execution and a vector floating-point unit (particularly suited to 3D graphics). Standard chips based on the SH-4 were introduced around 1998.
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