computer science

Super Harvard Architecture Single-Chip Computer

Super Harvard Architecture Single-Chip Computer is a computer science topic covered in the lgStudy science library. This page brings together a partial reference excerpt, illustrations, worked examples, real-world applications and a short study plan, so you can understand Super Harvard Architecture Single-Chip Computer rather than just read about it. In short: The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floating-point and fixed-point DSP from Analog Devices. SHARC is used in a variety of signal processing applications ranging from audio processing, to single-CPU guided artillery shells to 1000-CPU over-the-horizon radar processing computers.

Key takeaways

Super Harvard Architecture Single-Chip Computer belongs to computer science; place it in that map before memorising details.
Learn the definition first, then one example that makes the definition concrete.
Connect Super Harvard Architecture Single-Chip Computer to a quantity you can measure, compute or draw — that is where exam questions come from.
Reproduce the core statement of Super Harvard Architecture Single-Chip Computer from memory before moving on to harder problems.

Reference excerpt

The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floating-point and fixed-point DSP from Analog Devices. SHARC is used in a variety of signal processing applications ranging from audio processing, to single-CPU guided artillery shells to 1000-CPU over-the-horizon radar processing computers. The original design dates to about January 1994. SHARC processors are typically intended to have a good number of serial links to other SHARC processors nearby, to be used as a low-cost alternative to SMP.

Architecture The SHARC is a Harvard architecture word-addressed VLIW processor; it knows nothing of 8-bit or 16-bit values since each address is used to point to a whole 32-bit word, not just an octet. It is thus neither little-endian nor big-endian, though a compiler may use either convention if it implements 64-bit data and/or some way to pack multiple 8-bit or 16-bit values into a single 32-bit word. In C, the characters are 32-bit as they are the smallest addressable words in the architecture. The word size is 48-bit for instructions, 32-bit for integers and normal floating-point, and 40-bit for extended floating-point. Code and data are normally fetched from on-chip memory, which the user must split into regions of different word sizes as desired. Small data types may be stored in wider memory, simply wasting the extra space. A system that does not use 40-bit extended floating-point might divide the on-chip memory into two sections, a 48-bit one for code and a 32-bit one for everything else. Most memory-related CPU instructions can not access all the bits of 48-bit memory, but a special 48-bit register is provided for this purpose. The special 48-bit register may be accessed as a pair of smaller registers, allowing movement to and from the normal registers. Off-chip memory can be used with the SHARC. This memory can only be configured for one single size. If the off-chip memory is configured as 32-bit words to avoid waste, then only the on-chip memory may be used for code execution and extended floating-point. Operating systems may use overlays to work around this problem, transferring 48-bit data to on-chip memory as needed for execution. A DMA engine is provided for this. True paging is impossible without an external MMU. The SHARC has a 32-bit word-addressed address space. Depending on word size this is 16 GB, 20 GB, or 24 GB (using the common definition of an 8-bit "byte"). SHARC instructions may contain a 32-bit immediate operand. Instructions without this operand are generally able to perform two or more operations simultaneously. Many instructions are conditional, and may be preceded with "if condition " in the assembly language. There are a number of condition choices, similar to the choices provided by the x86 flags register. There are two delay slots. After a jump, two instructions following the jump will normally be executed. The SHARC processor has built-in support for loop control. Up to 6 levels may be used, avoiding the need for normal branching instructions and the normal bookkeeping related to loop exit. The SHARC has two full sets of general-purpose registers. Code can instantly switch between them, allowing for fast context switches between an application and an OS or between two threads.

Software support Compilers:

Analog Devices CrossCore compiler (commercial) Analog Devices Visual DSP++ (commercial) Analog Devices g21k, a defunct fork of GCC (GPLv2)

See also TigerSHARC – parallel descendant from Analog Devices Blackfin – modern (2000–) replacement from Analog Devices Qualcomm Hexagon – competitor Texas Instruments TMS320 – competitor CEVA, Inc. – competitor

References

External links SHARC processors website

Worked examples

Example 1 — a first encounter with Super Harvard Architecture Single-Chip Computer

Start with the simplest possible case. Write down what Super Harvard Architecture Single-Chip Computer claims or describes in one sentence, then invent the smallest concrete situation in which that sentence is true. In computer science, the smallest case is usually a single object, a single equation or a single measurement. Check that every symbol or term in your sentence has a meaning in that case.

Example 2 — changing one variable

Take the situation from Example 1 and change exactly one quantity: double it, halve it, or set it to zero. Predict what should happen to Super Harvard Architecture Single-Chip Computer before you calculate. Comparing your prediction with the result is the fastest way to find out whether you understand the idea or only the words.

Example 3 — an exam-style question

Typical questions about Super Harvard Architecture Single-Chip Computer ask you to (a) state it precisely, (b) apply it to given data, and (c) explain a limitation. Practise writing all three answers in under five minutes; the third part is what separates a full-mark answer from an average one.

Applications of Super Harvard Architecture Single-Chip Computer

In research: Super Harvard Architecture Single-Chip Computer appears in computer science research whenever the underlying quantities have to be modelled precisely. Papers usually cite it as a starting assumption and then explore where it breaks down.
In technology and industry: Engineering practice reuses Super Harvard Architecture Single-Chip Computer in design rules, simulations and safety margins. Knowing the idea lets you read a specification sheet and understand why the numbers look the way they do.
In the classroom: Super Harvard Architecture Single-Chip Computer is common in secondary-school and first-year university syllabi. It links to neighbouring topics Digital signal processors, VLIW microprocessors, Very long instruction word computing, so understanding it makes those chapters shorter.
In everyday life: Look for Super Harvard Architecture Single-Chip Computer outside the textbook — in sport, cooking, traffic, electronics or the sky above you. An example you found yourself is remembered far longer than one you were given.

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How to study Super Harvard Architecture Single-Chip Computer in 20 minutes

Read the reference excerpt below once, without taking notes.
Close the page and write down what Super Harvard Architecture Single-Chip Computer means in your own words.
Compare your version with the excerpt and mark what you missed.
Work through the three examples above with pen and paper.
Explain Super Harvard Architecture Single-Chip Computer out loud to somebody else — or to Teacher Smith in the lgStudy chat.

Frequently asked questions

What is Super Harvard Architecture Single-Chip Computer in simple terms?

Why does Super Harvard Architecture Single-Chip Computer matter?

Because it connects several computer science ideas at once: it gives you a definition you can apply, a quantity you can calculate, and a way to check whether a result is plausible.

How should I study Super Harvard Architecture Single-Chip Computer?

Read the excerpt, restate it from memory, then work through the examples and applications listed on this page. The five-step study plan above takes about twenty minutes.

What does this page cover?

It gives you a compact reference excerpt plus original lgStudy explanations, examples, applications and study material on Super Harvard Architecture Single-Chip Computer.