SystemC

Key takeaways

SystemC belongs to science; place it in that map before memorising details.
Learn the definition first, then one example that makes the definition concrete.
Connect SystemC to a quantity you can measure, compute or draw — that is where exam questions come from.
Reproduce the core statement of SystemC from memory before moving on to harder problems.

Reference excerpt

SystemC is a set of C++ classes and macros which provide an event-driven simulation interface (see also discrete event simulation). These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax. SystemC processes can communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the hardware description languages VHDL and Verilog, but is more aptly described as a system-level modeling language. SystemC is applied to system-level modeling, architectural exploration, performance modeling, software development, functional verification, and high-level synthesis. SystemC is often associated with electronic system-level (ESL) design, and with transaction-level modeling (TLM).

Language specification SystemC is defined and promoted by the Open SystemC Initiative (OSCI — now Accellera), and has been approved by the IEEE Standards Association as IEEE 1666-2011 - the SystemC Language Reference Manual (LRM). The LRM provides the definitive statement of the semantics of SystemC. OSCI also provide an open-source proof-of-concept simulator (sometimes incorrectly referred to as the reference simulator), which can be downloaded from the OSCI website. Although it was the intent of OSCI that commercial vendors and academia could create original software compliant to IEEE 1666, in practice most SystemC implementations have been at least partly based on the OSCI proof-of-concept simulator.

Compared to HDLs SystemC has semantic similarities to VHDL and Verilog, but may be said to have a syntactical overhead compared to these when used as a hardware description language. On the other hand, it offers a greater range of expression, similar to object-oriented design partitioning and template classes. Although strictly a C++ class library, SystemC is sometimes viewed as being a language in its own right. Source code can be compiled with the SystemC library (which includes a simulation kernel) to give an executable. The performance of the OSCI open-source implementation is typically worse than commercial VHDL/Verilog simulators when used for register transfer level simulation.

Versions SystemC version 1 included common hardware-description language features such as structural hierarchy and connectivity, clock-cycle accuracy, delta cycles, four-valued logic (0, 1, X, Z), and bus-resolution functions. SystemC version 2 onward focused on communication abstraction, transaction-level modeling, and virtual-platform modeling. It also added abstract ports, dynamic processes, and timed event notifications.

Language features

Modules SystemC has a notion of a container class called a module. This is a hierarchical entity that can have other modules or processes contained in it. Modules are the basic building blocks of a SystemC design hierarchy. A SystemC model usually consists of several modules which communicate via ports. The modules can be thought of as a building block of SystemC.

Ports Ports allow communication from inside a module to the outside (usually to other modules) via channels.

Signals SystemC supports resolved and unresolved signals. Resolved signals can have more than one driver (a bus) while unresolved signals can have only one driver.

Exports Modules have ports through which they connect to other modules. SystemC supports single-direction and bidirectional ports. Exports incorporate channels and allow communication from inside a module to the outside (usually to other modules).

Processes Processes are used to describe functionality. Processes are contained inside modules. SystemC provides three different process abstractions to be used by hardware and software designers. Processes are the main computation elements. They are concurrent.

Channels Channels are the communication elements of SystemC. They can be either simple wires or complex communication mechanisms like FIFOs or bus channels. Elementary channels:

signal: the equivalent of a wire buffer fifo mutex semaphore

Interfaces Ports use interfaces to communicate with channels.

Events Events allow synchronization between processes and must be defined during initialization.

Data types SystemC introduces several data types which support the modeling of hardware. Extended standard types:

sc_int<n> n-bit signed integer sc_uint<n> n-bit unsigned integer sc_bigint<n> n-bit signed integer for n > 64 sc_biguint<n> n-bit unsigned integer for n > 64 Logic types:

sc_bit 2-valued single bit sc_logic 4-valued single bit sc_bv<n> vector of length n of sc_bit sc_lv<n> vector of length n of sc_logic Fixed point types:

sc_fixed<> templated signed fixed point sc_ufixed<> templated unsigned fixed point sc_fix untemplated signed fixed point sc_ufix untemplated unsigned fixed point

History 1999-09-27 Open SystemC Initiative announced 2000-03-01 SystemC V0.91 released 2000-03-28 SystemC V1.0 released 2001-02-01 SystemC V2.0 specification and V1.2 Beta source code released 2003-06-03 SystemC 2.0.1 LRM (language reference manual) released 2005-06-06 SystemC 2.1 LRM and TLM 1.0 transaction-level modeling standard released 2005-12-12 IEEE approves the IEEE 1666–2005 standard for SystemC 2007-04-13 SystemC v2.2 released 2008-06-09 TLM-2.0.0 library released 2009-07-27 TLM-2.0 LRM released, accompanied by TLM-2.0.1 library 2010-03-08 SystemC AMS extensions 1.0 LRM released 2011-11-10 IEEE approves the IEEE 1666–2011 standard for SystemC 2016-04-06 IEEE approves the IEEE 1666.1–2016 standard for SystemC AMS 2023-06-05 IEEE approves the IEEE 1666–2023 standard SystemC traces its origins to work on Scenic programming language described in a DAC 1997 paper. ARM Ltd., CoWare, Synopsys and CynApps teamed up to develop SystemC (CynApps later became Forte Design Systems) to launch it first draft version in 1999. The chief competitor at the time was SpecC another C based open source package developed by UC Irvine personnel and some Japanese companies. In June 2000, a standards group known as the Open SystemC Initiative was formed to provide an industry neutral organization to host SystemC activities and to allow Synopsys' largest competitors, Cadence and Mentor Graphics, democratic representation in SystemC development.

Example code Example code of an adder:

… excerpt ends here. Continue reading the full article.

Worked examples

Example 1 — a first encounter with SystemC

Start with the simplest possible case. Write down what SystemC claims or describes in one sentence, then invent the smallest concrete situation in which that sentence is true. In science, the smallest case is usually a single object, a single equation or a single measurement. Check that every symbol or term in your sentence has a meaning in that case.

Example 2 — changing one variable

Take the situation from Example 1 and change exactly one quantity: double it, halve it, or set it to zero. Predict what should happen to SystemC before you calculate. Comparing your prediction with the result is the fastest way to find out whether you understand the idea or only the words.

Example 3 — an exam-style question

Typical questions about SystemC ask you to (a) state it precisely, (b) apply it to given data, and (c) explain a limitation. Practise writing all three answers in under five minutes; the third part is what separates a full-mark answer from an average one.

Applications of SystemC

In research: SystemC appears in science research whenever the underlying quantities have to be modelled precisely. Papers usually cite it as a starting assumption and then explore where it breaks down.
In technology and industry: Engineering practice reuses SystemC in design rules, simulations and safety margins. Knowing the idea lets you read a specification sheet and understand why the numbers look the way they do.
In the classroom: SystemC is common in secondary-school and first-year university syllabi. It links to neighbouring topics C++ programming language family, Hardware description languages, Hardware verification languages, so understanding it makes those chapters shorter.
In everyday life: Look for SystemC outside the textbook — in sport, cooking, traffic, electronics or the sky above you. An example you found yourself is remembered far longer than one you were given.

How to study SystemC in 20 minutes

Read the reference excerpt below once, without taking notes.
Close the page and write down what SystemC means in your own words.
Compare your version with the excerpt and mark what you missed.
Work through the three examples above with pen and paper.
Explain SystemC out loud to somebody else — or to Teacher Smith in the lgStudy chat.

Frequently asked questions

What is SystemC in simple terms?

SystemC is a set of C++ classes and macros which provide an event-driven simulation interface (see also discrete event simulation). These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax.

Why does SystemC matter?

Because it connects several science ideas at once: it gives you a definition you can apply, a quantity you can calculate, and a way to check whether a result is plausible.

How should I study SystemC?

Read the excerpt, restate it from memory, then work through the examples and applications listed on this page. The five-step study plan above takes about twenty minutes.

What does this page cover?

It gives you a compact reference excerpt plus original lgStudy explanations, examples, applications and study material on SystemC.