The Transmeta Crusoe is a family of x86-compatible microprocessors developed by Transmeta and introduced in 2000. Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction layer, or a virtual machine, known as the Code Morphing Software (CMS). The CMS translates machine code instructions received from programs into native instructions for the microprocessor. In this way, the Crusoe can emulate other instruction set architectures (ISAs). This is used to allow the microprocessors to emulate the Intel x86 instruction set.
Design
The Crusoe is notable for its method of achieving x86 compatibility. Instead of the instruction set architecture being implemented in hardware, or translated by specialized hardware, the Crusoe runs a software abstraction layer, or a virtual machine, known as the Code Morphing Software (CMS). The CMS translates machine code instructions received from programs into native instructions for the microprocessor. In this way, the Crusoe can emulate other instruction set architectures (ISAs). This is used to allow the microprocessors to emulate the Intel x86 instruction set. In theory, it is possible for the CMS to be modified to emulate other ISAs. Transmeta demonstrated Crusoe executing Java bytecode by translating the bytecodes into instructions in its native instruction set. The addition of an abstraction layer between the x86 instruction stream and the hardware means that the hardware architecture can change without breaking compatibility, just by modifying the CMS. For example, Transmeta Efficeon — a second-generation Transmeta design — has a 256-bit-wide VLIW core versus the 128-bit core of the Crusoe. Efficeon also supports SSE instructions. The Crusoe is a VLIW microprocessor that executes bundles of instructions, termed molecules by Transmeta. Each molecule contains multiple instructions, termed atoms. The Code Morphing Software translates x86 instructions into native instructions. The native instructions are 32 bits long. Instructions that meet a set of conditions can be executed simultaneously and are combined to form a 64- or 128-bit molecule containing two or four atoms, respectively. In the event that there are not enough instructions to fill a molecule, the software inserts NOPs as padding to fill out empty slots. This is required in all VLIW architectures and is criticised for being inefficient, which is why there are molecules of two separate lengths. The Crusoe performs in software some of the functionality traditionally implemented in hardware (e.g. instruction re-ordering), resulting in simpler hardware with fewer transistors. The relative simplicity of the hardware means that Crusoe consumes less power (and therefore generates less heat) than other x86-compatible microprocessors running at the same frequency. A 700 MHz Crusoe ran x86 programs at the speed of a 500 MHz Pentium III x86 processor, although the Crusoe processor was smaller and cheaper than the corresponding Intel processor. The Crusoe was initially available in two forms: the TM3120 (later called TM3200) for embedded applications and the TM5400 for low-power personal computing. Both were based on the same architecture but differed in clock frequency and peripheral support. The TM3120/TM3200 were manufactured in speeds of 333 (TM3120 only), 366, and 400 MHz using a 220 nm process. It has a 96k L1 cache (64 KB instruction and 32 KB data) and no L2 cache. The TM3120/TM3200 has an integrated SDRAM memory controller and a PCI interface. It measures 77 mm2 and uses a 1.5 V power supply, dissipating less than 1.5 W of power (typically). The TM5400 differs from the TM3120/TM3200 with the inclusion of 128K of L1 Cache (with the addition of 32 KB data cache) as well as the addition of DDR memory support, 256 KB unified L2 cache and LongRun power reduction technology manufactured using a smaller 180 nm process. It measures 73 mm2 and uses a 1.10 V (f = 25%) and 1.6 V (f = 100%) power supply, dissipating 0.5–1.5 W typically and a maximum of 6 W. Later the TM5600 was introduced as a higher end offering to the TM5400 with double the L2 cache (512 KB vs 256 KB). Both the TM5400 and TM5600 operated at clock frequencies of 500–700 MHz. The TM5500/TM5800 are die shrunk versions of the TM5400/5600 Built on a TSMC 130 nm process at clock frequencies of 667-1000 MHz. Embedded versions rated for 10 years of continuous use were marketed as Crusoe SE (for Special Embedded) TM55E/TM58E respectively at clock frequencies of 667-993 MHz. The TM5700/TM5900 removes SDRAM support for its integrated memory controller and now comes in a 54% smaller 399 pin FC-OBGA package rather than the ceramic 479 BGA package used previously. Clock speed remains the same between 667 and 1000 MHz.
Production Transmeta was a fabless semiconductor company, without the facilities to fabricate their designs. Instead, both processors were fabricated by IBM Microelectronics, the semiconductor business of IBM. IBM fabricated the Crusoe in a 0.18 μm CMOS process with five levels of copper interconnect.
Software limitations The Crusoe processor supports MMX but not SSE. As of 2022, most browsers on Windows and Linux, and some other programs, need SSE or SSE2 support; therefore, that software will no longer run on the Crusoe platform. For example, Firefox dropped support for systems without SSE2 in 2017, although K-Meleon could run without SSE on Windows XP. The Efficeon processor added support for SSE and SSE2.
Products
References
Further reading Halfhill, Tom R. (14 February 2000). "Transmeta Breaks x86 Low-Power Barrier". Microprocessor Report. Halfhill, Tom R. (10 July 2000). "Top PC Vendors Adopt Crusoe". Microprocessor Report.
External links Linux on laptops and notebooks with Transmeta CPUs at the Wayback Machine (archived 2017-12-29) Crusoe Exposed: Transmeta TM5xxx Architecture 1 Crusoe Exposed: Transmeta TM5xxx Architecture 2 Transmeta: Are the chips down?
