astronomy

Universal Verification Methodology

Universal Verification Methodology is a astronomy topic covered in the lgStudy science library. This page brings together a partial reference excerpt, illustrations, worked examples, real-world applications and a short study plan, so you can understand Universal Verification Methodology rather than just read about it. In short: The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e verification language developed by Verisity Design in 2001.

Key takeaways

Universal Verification Methodology belongs to astronomy; place it in that map before memorising details.
Learn the definition first, then one example that makes the definition concrete.
Connect Universal Verification Methodology to a quantity you can measure, compute or draw — that is where exam questions come from.
Reproduce the core statement of Universal Verification Methodology from memory before moving on to harder problems.

Reference excerpt

The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e verification language developed by Verisity Design in 2001. The UVM class library brings a framework and automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by EDA (Electronic Design Automation) Vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics(Siemens), Synopsys, Xilinx Simulator(XSIM).

History In December 2009, a technical subcommittee of Accellera — a standards organization in the electronic design automation (EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1), a verification methodology developed jointly in 2007 by Cadence Design Systems and Mentor Graphics. On February 21, 2011, Accellera approved the 1.0 version of UVM. UVM 1.0 includes a Reference Guide, a Reference Implementation in the form of a SystemVerilog base class library, and a User Guide.

Language features

Factory A factory is a commonly used concept in object-oriented programming. It is an object that is used for instantiating other objects. There are two ways to register an object with the UVM factory. In the declaration of class A, one can invoke the `uvm_object_utils(A) or `uvm_component_utils(A) registration macros. Otherwise, the `uvm_object_registry(A,B) or `uvm_component_registry(A,B) macros can be used to map a string B to a class type A. The UVM factory provides a variety of create methods that allow the user to instantiate an object with a particular instance name and of a registered type.

Sequencer The sequencer is responsible for three main functions:

Put the DUT (Design Under Test) and the verification environment into an initialization state Configuring the verification environment and DUT The entire DUT scenario generation

Initialization In this stage the DUT (Design Under Test) and the test bench environment should be set to the desired initial conditions. Usually this includes:

Loading memory, with any type of needed initial conditions Initial pin settings on the DUT, such as power and high-impedance Register settings that can not be altered during simulation such as mode bits or portions of the environment registers Verification component settings that can not be altered during simulation

Scoreboard

Description A scoreboard can be implemented in various ways. Generally speaking, a scoreboard takes the inputs to and outputs from the DUT, determines what the input-output relationship should be, and judges whether the DUT adheres to the specification. This input-output relationship is often specified by a model, called a predictor. The predictor may be implemented in a higher-level programming language, like SystemC.

Implementation Details UVM scoreboard classes are implemented as subclasses of the uvm_scoreboard class, which itself is a subclass of uvm_component. uvm_scoreboard is a blank slate for implementing a scoreboard. It only contains one class method, namely the "new" constructor method. The rest of the implementation is user-defined.

Agent

Description In modern VLSI, a DUT may have multiple interfaces. Each of these interfaces may have different UVM objects associated with them. For instance, if the DUT is the full-chip, there may be separate interfaces for PCI, Ethernet, and other communication standards. The scoreboard and monitor for a PCI interface will be different from the ones for the Ethernet interface. The various UVM objects can be organized as members of a wrapper class known as an agent. Passive agents will only analyze port values of the interface and should contain a monitor member. Active agents will drive ports and should contain a driver member, perhaps in addition to a monitor member.

Implementation Details UVM agent classes are implemented as subclasses of the uvm_agent class, which itself is a subclass of uvm_component. Much like uvm_scoreboard, uvm_agent is lightweight in terms of class methods. Its only class methods are the "new" constructor and the "get_is_active" method. If the agent is being used to drive ports, get_is_active returns UVM_ACTIVE. Otherwise, get_is_active returns UVM_PASSIVE.

Driver

Description Sequence items for a test are described abstractly. For example, if the DUT is a register file, it may have ports for a read address and a write address. The sequence item object may have member variables for the read address and the write address. However, these values need to eventually become bits at the input pins to the DUT. There may even be an exotic encoding used when providing the stimulus to the DUT that should be abstracted from the rest of the agent. The driver's responsibility is to take these sequence items and provide the proper stimulus to the DUT's ports.

Implementation Details UVM driver classes are implemented as subclasses of the uvm_driver class, which itself is a subclass of uvm_component.

Definitions Agent - A container that emulates and verifies DUT devices Blocking - An interface that blocks tasks from other interfaces until it completes DUT - Device under test, what you are actually testing DUV - Device Under Verification Component - A portion of verification intellectual property that has interfaces and functions. Transactor - see component Verification Environment Configuration - those settings in the DUT and environment that are alterable while the simulation is running VIP - Verification Intellectual Property

UVM Macros UVM allows the use of Macros

References

External links

Official Universal Verification Methodology (UVM) Working Group, Accellera 1800.2-2020 - IEEE Standard for Universal Verification Methodology Language Reference Manual, IEEE, 14 September, 2020 UVM 1.2 Class Reference, Mentor Graphics, Cadence Design Systems, Synopsys and Nvidia, 2014. (Superseded by IEEE specification above).

Guides UVM Verification Primer, Doulos, June 2010 Accellera UVM: Ready, Set, Deploy!, Accellera, February 27, 2012 EDA Playground - run UVM simulations from a web browser (free online IDE) What's New in SystemVerilog UVM 1.2, EDA Playground, YouTube channel, 2014

Worked examples

Example 1 — a first encounter with Universal Verification Methodology

Start with the simplest possible case. Write down what Universal Verification Methodology claims or describes in one sentence, then invent the smallest concrete situation in which that sentence is true. In astronomy, the smallest case is usually a single object, a single equation or a single measurement. Check that every symbol or term in your sentence has a meaning in that case.

Example 2 — changing one variable

Take the situation from Example 1 and change exactly one quantity: double it, halve it, or set it to zero. Predict what should happen to Universal Verification Methodology before you calculate. Comparing your prediction with the result is the fastest way to find out whether you understand the idea or only the words.

Example 3 — an exam-style question

Typical questions about Universal Verification Methodology ask you to (a) state it precisely, (b) apply it to given data, and (c) explain a limitation. Practise writing all three answers in under five minutes; the third part is what separates a full-mark answer from an average one.

Applications of Universal Verification Methodology

In research: Universal Verification Methodology appears in astronomy research whenever the underlying quantities have to be modelled precisely. Papers usually cite it as a starting assumption and then explore where it breaks down.
In technology and industry: Engineering practice reuses Universal Verification Methodology in design rules, simulations and safety margins. Knowing the idea lets you read a specification sheet and understand why the numbers look the way they do.
In the classroom: Universal Verification Methodology is common in secondary-school and first-year university syllabi. It links to neighbouring topics Electronic design automation, so understanding it makes those chapters shorter.
In everyday life: Look for Universal Verification Methodology outside the textbook — in sport, cooking, traffic, electronics or the sky above you. An example you found yourself is remembered far longer than one you were given.

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How to study Universal Verification Methodology in 20 minutes

Read the reference excerpt below once, without taking notes.
Close the page and write down what Universal Verification Methodology means in your own words.
Compare your version with the excerpt and mark what you missed.
Work through the three examples above with pen and paper.
Explain Universal Verification Methodology out loud to somebody else — or to Teacher Smith in the lgStudy chat.

Frequently asked questions

What is Universal Verification Methodology in simple terms?

Why does Universal Verification Methodology matter?

Because it connects several astronomy ideas at once: it gives you a definition you can apply, a quantity you can calculate, and a way to check whether a result is plausible.

How should I study Universal Verification Methodology?

Read the excerpt, restate it from memory, then work through the examples and applications listed on this page. The five-step study plan above takes about twenty minutes.

What does this page cover?

It gives you a compact reference excerpt plus original lgStudy explanations, examples, applications and study material on Universal Verification Methodology.