Dynamic frequency scaling and dynamic voltage scaling are techniques used primarily for power management in computer architecture. Dynamic frequency scaling almost always appears in conjunction with dynamic voltage scaling, since higher frequencies require higher supply voltages for the digital circuit to yield correct results. The combined topic is known as dynamic voltage and frequency scaling (DVFS).
Dynamic frequency scaling Dynamic frequency scaling (also known as CPU throttling) is a power management technique in computer architecture whereby the frequency of a microprocessor can be automatically adjusted "on the fly" depending on the actual needs, to conserve power and reduce the amount of heat generated by the chip. Dynamic frequency scaling helps preserve battery on mobile devices and decrease cooling cost and noise on quiet computing settings, or can be useful as a security measure for overheated systems (e.g. after poor overclocking).
Operation
The dynamic power (switching power) dissipated by a chip is C·V2·A·f, where C is the capacitance being switched per clock cycle, V is voltage, A is the activity factor indicating the average number of switching events per clock cycle by the transistors in the chip (as a unitless quantity) and f is the clock frequency. Voltage is therefore the main determinant of power usage and heating. The voltage required for stable operation is determined by the frequency at which the circuit is clocked, and can be reduced if the frequency is also reduced. Dynamic power alone does not account for the total power of the chip, however, as there is also static power, which is primarily because of various leakage currents. Due to static power consumption and asymptotic execution time it has been shown that the energy consumption of software shows convex energy behavior, i.e., there exists an optimal CPU frequency at which energy consumption is minimized. Leakage current has become more and more important as transistor sizes have become smaller and threshold voltage levels are reduced. A decade ago, dynamic power accounted for approximately two-thirds of the total chip power. The power loss due to leakage currents in contemporary CPUs and SoCs tend to dominate the total power consumption. In the attempt to control the leakage power, high-k metal-gates and power gating have been common methods. Dynamic voltage scaling is another related power conservation technique that is often used in conjunction with frequency scaling, as the frequency that a chip may run at is related to the operating voltage. The efficiency of some electrical components, such as voltage regulators, decreases with increasing temperature, so the power usage may increase with temperature. Since increasing power use may increase the temperature, increases in voltage or frequency may increase system power demands even further than the CMOS formula indicates, and vice versa.
Standard interface ACPI 1.0 (1996) defines a way for a CPU to go to idle "C states", but defines no frequency-scaling system. ACPI 2.0 (2000) introduces a system of P states (power-performance states) that a processor can use to communicate its possible frequency–power settings to the OS. The operating system then sets the speed as needed by switching between these states. Throttling technology such as SpeedStep, PowerNow!/Cool'n'Quiet, and PowerSaver all work through P states. There is a limit of 16 states maximum. ACPI 5.0 (2011) introduces collaborative processor performance control (CPPC), exposing hundreds of performance levels to the OS for selection in the form of a "performance level" abstracted away from the frequency. This abstraction provides leeway for the processor to adjust its workings (C-states) in ways other than just the frequency (P-states).
Autonomous frequency scaling A number of modern CPUs can perform frequency scaling autonomously, using a performance level range and a "efficiency/performance preference" hint from the OS.
Intel CPUs starting with Skylake support hardware-managed P-states aka Speed Shift, It based on CPPC protocol, and it using model-specific register as the control channel. AMD CPUs starting with Zen 2 supports a similar feature. It depends on CPPC being enabled. The preferred communication channel is a MSR (different from the Intel one) introduced in Zen 3; Zen 2 units use the ACPI AML method.
Performance impact Dynamic frequency scaling reduces the number of instructions a processor can issue in a given amount of time, thus reducing performance. Hence, it is generally used when the workload is not CPU-bound. Dynamic frequency scaling by itself is rarely worthwhile as a way to conserve switching power. Saving the highest possible amount of power requires dynamic voltage scaling too, because of the V2 component and the fact that modern CPUs are strongly optimized for low power idle states. In most constant-voltage cases, it is more efficient to run briefly at peak speed and stay in a deep idle state for longer time (called "race to idle" or computational sprinting), than it is to run at a reduced clock rate for a long time and only stay briefly in a light idle state. However, reducing voltage along with clock rate can change those trade-offs. A related-but-opposite technique is overclocking, whereby processor performance is increased by ramping the processor's (dynamic) frequency beyond the manufacturer's design specifications. One major difference between the two is that in modern PC systems overclocking is mostly done over the Front Side Bus (mainly because the multiplier is normally locked), but dynamic frequency scaling is done with the multiplier. Moreover, overclocking is often static, while dynamic frequency scaling is always dynamic. Software can often incorporate overclocked frequencies into the frequency scaling algorithm, if the chip degradation risks are allowable.
Support across vendors
Intel Intel's CPU throttling technology, SpeedStep, is used in its mobile and desktop CPU lines.
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