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Wishbone (computer bus)

Wishbone (computer bus) is a computer science topic covered in the lgStudy science library. This page brings together a partial reference excerpt, illustrations, worked examples, real-world applications and a short study plan, so you can understand Wishbone (computer bus) rather than just read about it. In short: The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip.

Wishbone (computer bus) — main illustration
Wishbone (computer bus) — illustration

Key takeaways

  • Wishbone (computer bus) belongs to computer science; place it in that map before memorising details.
  • Learn the definition first, then one example that makes the definition concrete.
  • Connect Wishbone (computer bus) to a quantity you can measure, compute or draw — that is where exam questions come from.
  • Reproduce the core statement of Wishbone (computer bus) from memory before moving on to harder problems.

Reference excerpt

The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores project. Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels. This ambiguity is intentional. Wishbone is made to let designers combine several designs written in Verilog, VHDL or some other logic-description language for electronic design automation (EDA). Wishbone provides a standard way for designers to combine these hardware logic designs (called "cores"). Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated combinatorially for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags. Wishbone is open source. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of prior art, to prove its concepts are in the public domain. A device does not conform to the Wishbone specification unless it includes a data sheet that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others. The Simple Bus Architecture is a simplified version of the Wishbone specification.

Wishbone topologies Wishbone adapts well to common topologies such as point-to-point, many-to-many (i.e. the classic bus system), hierarchical, or even switched fabrics such as crossbar switches. In the more exotic topologies, Wishbone requires a bus controller or arbiter, but devices still maintain the same interface.

Shared bus

Data flow

Crossbar switch

Comparisons

Wishbone control signals are compared to other system on a chip (SoC) bus standards in the below table:

See also Master/slave (technology) Advanced eXtensible Interface

Notes

References "SBA - Simple Bus Architecture". sba.accesus.com. 2015. Miti, Milica; Stojcev, Mile (2006). "An Overview of On-Chip Buses". Facta Universitatis - Series: Electronics and Energetics. 19 (3): 405–428. doi:10.2298/FUEE0603405M – via ResearchGate. Wishbone B4: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores (PDF), OpenCores, 2010, archived (PDF) from the original on May 18, 2025

External links Wishbone Version B3- An older revision of the specification appnote_01- Combining WISHBONE interface signals application note Comparison to other SoC buses Wishbone@OpenCores Wishbone@FPGA-Cores.com

Illustrations

Wishbone (computer bus): Master and Slave Wishbone's interfaces.
Master and Slave Wishbone's interfaces.
Wishbone (computer bus) illustration
Wishbone (computer bus) illustration
Wishbone (computer bus) illustration

Worked examples

Example 1 — a first encounter with Wishbone (computer bus)

Start with the simplest possible case. Write down what Wishbone (computer bus) claims or describes in one sentence, then invent the smallest concrete situation in which that sentence is true. In computer science, the smallest case is usually a single object, a single equation or a single measurement. Check that every symbol or term in your sentence has a meaning in that case.

Example 2 — changing one variable

Take the situation from Example 1 and change exactly one quantity: double it, halve it, or set it to zero. Predict what should happen to Wishbone (computer bus) before you calculate. Comparing your prediction with the result is the fastest way to find out whether you understand the idea or only the words.

Example 3 — an exam-style question

Typical questions about Wishbone (computer bus) ask you to (a) state it precisely, (b) apply it to given data, and (c) explain a limitation. Practise writing all three answers in under five minutes; the third part is what separates a full-mark answer from an average one.

Applications of Wishbone (computer bus)

In research
Wishbone (computer bus) appears in computer science research whenever the underlying quantities have to be modelled precisely. Papers usually cite it as a starting assumption and then explore where it breaks down.
In technology and industry
Engineering practice reuses Wishbone (computer bus) in design rules, simulations and safety margins. Knowing the idea lets you read a specification sheet and understand why the numbers look the way they do.
In the classroom
Wishbone (computer bus) is common in secondary-school and first-year university syllabi. It links to neighbouring topics Computer buses, Open hardware electronic devices, so understanding it makes those chapters shorter.
In everyday life
Look for Wishbone (computer bus) outside the textbook — in sport, cooking, traffic, electronics or the sky above you. An example you found yourself is remembered far longer than one you were given.
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How to study Wishbone (computer bus) in 20 minutes

  1. Read the reference excerpt below once, without taking notes.
  2. Close the page and write down what Wishbone (computer bus) means in your own words.
  3. Compare your version with the excerpt and mark what you missed.
  4. Work through the three examples above with pen and paper.
  5. Explain Wishbone (computer bus) out loud to somebody else — or to Teacher Smith in the lgStudy chat.

Frequently asked questions

What is Wishbone (computer bus) in simple terms?

The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip.

Why does Wishbone (computer bus) matter?

Because it connects several computer science ideas at once: it gives you a definition you can apply, a quantity you can calculate, and a way to check whether a result is plausible.

How should I study Wishbone (computer bus)?

Read the excerpt, restate it from memory, then work through the examples and applications listed on this page. The five-step study plan above takes about twenty minutes.

What does this page cover?

It gives you a compact reference excerpt plus original lgStudy explanations, examples, applications and study material on Wishbone (computer bus).

Tags

  • Computer buses
  • Open hardware electronic devices

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