computer science

Zero ASIC

Zero ASIC is a computer science topic covered in the lgStudy science library. This page brings together a partial reference excerpt, illustrations, worked examples, real-world applications and a short study plan, so you can understand Zero ASIC rather than just read about it. In short: Zero ASIC Corporation, formerly Adapteva, Inc., is a fabless semiconductor company focusing on low power many core microprocessor design. The company was the second company to announce a design with 1,000 specialized processing cores on a single integrated circuit.

Key takeaways

Zero ASIC belongs to computer science; place it in that map before memorising details.
Learn the definition first, then one example that makes the definition concrete.
Connect Zero ASIC to a quantity you can measure, compute or draw — that is where exam questions come from.
Reproduce the core statement of Zero ASIC from memory before moving on to harder problems.

Reference excerpt

Zero ASIC Corporation, formerly Adapteva, Inc., is a fabless semiconductor company focusing on low power many core microprocessor design. The company was the second company to announce a design with 1,000 specialized processing cores on a single integrated circuit. Adapteva was founded in 2008 with the goal of bringing a ten times advancement in floating-point performance per watt for the mobile device market. Products are based on its Epiphany multi-core multiple instruction, multiple data (MIMD) architecture and its Parallella Kickstarter project promoting "a supercomputer for everyone" in September 2012. The company's original name, Adapteva, is a combination of "adapt" and the Hebrew word "Teva" meaning nature. Sometime before October 2023 the company was renamed to Zero ASIC, with a distinct focus on chiplet-based products and FPGA design tools.

History Adapteva was founded in March 2008, by Andreas Olofsson. The company was founded with the goal of bringing a 10× advancement in floating-point processing energy efficiency for the mobile device market. In May 2009, Olofsson had a prototype of a new type of massively parallel multi-core computer architecture. The initial prototype was implemented in 65 nm and had 16 independent microprocessor cores. The initial prototypes enabled Adapteva to secure US$1.5 million in series-A funding from BittWare, a company from Concord, New Hampshire, in October 2009. Adapteva's first commercial chip product started sampling to customers in early May 2011 and they soon thereafter announced the capability to put up to 4,096 cores on a single chip. The Epiphany III, was announced in October 2011 using 28 nm and 65 nm manufacturing processes.

Products

Epiphany CPUs Adapteva's main product family is the Epiphany scalable multi-core MIMD architecture. The Epiphany architecture could accommodate chips with up to 4,096 RISC out-of-order microprocessors, all sharing a single 32-bit flat memory space. Each RISC processor in the Epiphany architecture is superscalar with 64× 32-bit unified register file (integer or single-precision) microprocessor operating up to 1 GHz and capable of 2 GFLOPS (single-precision). Epiphany's RISC processors use a custom instruction set architecture (ISA) optimised for single-precision floating-point, but are programmable in high level ANSI C using a standard GNU-GCC tool chain. Each RISC processor (in current implementations; not fixed in the architecture) has 32 KB of local memory. Code (possibly duplicated in each core) and stack space should be in that local memory; in addition (most) temporary data should fit there for full speed. Data can also be used from other processor cores local memory at a speed penalty, or off-chip RAM with much larger speed penalty. The memory architecture does not employ explicit hierarchy of hardware caches, similar to the Sony/Toshiba/IBM Cell processor, but with the additional benefit of off-chip and inter-core loads and stores being supported (which simplifies porting software to the architecture). It is a hardware implementation of partitioned global address space. This eliminated the need for complex cache coherency hardware, which places a practical limit on the number of cores in a traditional multicore system. The design allows the programmer to leverage greater foreknowledge of independent data access patterns to avoid the runtime cost of figuring this out. All processor nodes are connected through a network on chip, allowing efficient message passing.

Scalability The architecture is designed to scale almost indefinitely, with 4 e-links allowing multiple chips to be combined in a grid topology, allowing for systems with thousands of cores.

Coprocessors

On August 19, 2012, Adapteva posted some specifications and information about Epiphany multi-core coprocessors.

In September 2012, a 16-core version, the Epiphany-III (E16G301), was produced using 65 nm (11.5 mm2, 500 MHz chip) and engineering samples of 64-core Epiphany-IV (E64G401) were produced using 28 nm GlobalFoundries process (800 MHz). The primary markets for the Epiphany multi-core architecture include:

Smartphone applications such as real-time facial recognition, speech recognition, translation, and augmented reality. Next generation supercomputers requiring drastically better energy efficiency to allow systems to scale to exaflop computing levels. Floating-point acceleration in embedded systems based on field-programmable gate array architectures.

Parallella project

In September 2012, Adapteva started project Parallella on Kickstarter, which was marketed as "A Supercomputer for everyone." Architecture reference manuals for the platform were published as part of the campaign to attract attention to the project. The US$750,000 funding goal was reached in a month, with a minimum contribution of US$99 entitling backers to obtain one device; although the initial deadline was set for May 2013, the first single-board computers with 16-core Epiphany chip were finally shipped in December 2013. Size of board is planned to be 86 mm × 53 mm (3.4 in × 2.1 in). The Kickstarter campaign raised US$898,921. Raising US$3 million goal was unsuccessful, so no 64-core version of Parallella will be mass-produced. Kickstarter users having donated more than US$750 will get "parallella-64" variant with 64-core coprocessor (made from initial prototype manufacturing with 50 chips yield per wafer).

Epiphany V By 2016, the firm had taped out a 1024-core 64-bit variant of their Epiphany architecture that featured: larger local stores (64 KB), 64-bit addressing, double-precision floating-point arithmetic or SIMD single-precision, and 64-bit integer instructions, implemented in the 16 nm process node. This design included instruction set enhancements aimed at deep-learning and cryptography applications. In July 2017, Adapteva's founder became a DARPA MTO program manager and announced that the Epiphany V was "unlikely" to become available as a commercial product.

Performance The 16-core Parallella achieves roughly 5.0 GFLOPS/W, and the 64-core Epiphany-IV made with 28 nm estimated as 50 GFLOPS/W (single-precision), and 32-board system based on them achieves 15 GFLOPS/W. For comparison, top GPUs from AMD and Nvidia reached 10 GFLOPS/W for single-precision in 2009–2011 timeframe.

ChipMaker In 2023, the company pivoted to chiplet based CPU designs, using RISC-V CPU cores and open source FPGA design tools.

… excerpt ends here. Continue reading the full article.

Illustrations

Worked examples

Example 1 — a first encounter with Zero ASIC

Start with the simplest possible case. Write down what Zero ASIC claims or describes in one sentence, then invent the smallest concrete situation in which that sentence is true. In computer science, the smallest case is usually a single object, a single equation or a single measurement. Check that every symbol or term in your sentence has a meaning in that case.

Example 2 — changing one variable

Take the situation from Example 1 and change exactly one quantity: double it, halve it, or set it to zero. Predict what should happen to Zero ASIC before you calculate. Comparing your prediction with the result is the fastest way to find out whether you understand the idea or only the words.

Example 3 — an exam-style question

Typical questions about Zero ASIC ask you to (a) state it precisely, (b) apply it to given data, and (c) explain a limitation. Practise writing all three answers in under five minutes; the third part is what separates a full-mark answer from an average one.

Applications of Zero ASIC

In research: Zero ASIC appears in computer science research whenever the underlying quantities have to be modelled precisely. Papers usually cite it as a starting assumption and then explore where it breaks down.
In technology and industry: Engineering practice reuses Zero ASIC in design rules, simulations and safety margins. Knowing the idea lets you read a specification sheet and understand why the numbers look the way they do.
In the classroom: Zero ASIC is common in secondary-school and first-year university syllabi. It links to neighbouring topics American companies established in 2008, Companies based in Lexington, Massachusetts, Computer companies of the United States, so understanding it makes those chapters shorter.
In everyday life: Look for Zero ASIC outside the textbook — in sport, cooking, traffic, electronics or the sky above you. An example you found yourself is remembered far longer than one you were given.

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How to study Zero ASIC in 20 minutes

Read the reference excerpt below once, without taking notes.
Close the page and write down what Zero ASIC means in your own words.
Compare your version with the excerpt and mark what you missed.
Work through the three examples above with pen and paper.
Explain Zero ASIC out loud to somebody else — or to Teacher Smith in the lgStudy chat.

Frequently asked questions

What is Zero ASIC in simple terms?

Why does Zero ASIC matter?

Because it connects several computer science ideas at once: it gives you a definition you can apply, a quantity you can calculate, and a way to check whether a result is plausible.

How should I study Zero ASIC?

Read the excerpt, restate it from memory, then work through the examples and applications listed on this page. The five-step study plan above takes about twenty minutes.

What does this page cover?

It gives you a compact reference excerpt plus original lgStudy explanations, examples, applications and study material on Zero ASIC.